Search

Background: As semiconductor technologies continue to shrink, the growth in the number of process variables and combined effects tighten the overall process window, which leads to a more serious yield loss. Yield cannot be totally guaranteed by design rule check and verifications of optical proximity correction, due to complex process variations. The joint effects from unreasonable designs and unstable control of critical dimensions and overlay mainly contribute to the formation of bridging defects in critical interconnect layers. Aim: Our paper puts forward a model to detect the potential bridging region and predicts the corresponding failure probability under a litho-etch-litho-etch process. Approach: The proposed model is based on input error sources from variations of lithography and etch processes. In this scheme, bridging is expected when the minimum space of simulated postetch contours within a specific range is smaller than a user-defined bridging threshold. Gaussian distribution characteristics of line edge roughness (LER) and overlay are considered in the proposed model. Moreover, the proposed model provides meaningful guidelines for bridging prediction with the use of process variation bands. Results: The experiment results indicate consistency and validity of theoretical derivation of the proposed model. The concrete impacts of LER and overlay on the model have been quantitatively analyzed as well. Conclusions: According to the predicted probabilities, the model can early discover potential bridging defects quantitatively by considering the statistical properties of process variations with very few calculations and can give a ranking of failure severity as a decision foundation for design rule optimization. [ABSTRACT FROM AUTHOR]