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A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [19]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [42], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under 84Kr17+ exposure of 322.0 MeV at various flux condition from 1 × 103 to 5 × 105 count/cm2/sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage. [ABSTRACT FROM AUTHOR]

We present a high qualitative reconfigurability method for fault-tolerant memory systems against radiation influence on semiconductors. Its novelty lies in a joint failure repair mechanism. It uses a concurrent on-line technique based on asynchronous built-in current sensors (BICS), parity check and cold spare modules against electrical abnormal behaviour due to latch-up (LU), and the Hamming SEC code to counterattack single error upset (SEU), manifested in logical failures. Complete reliability computations, which underlie the proposed scheme, search for a 99.902% tolerance, thought to meet typical spatial irradiation conditions, to the cost of a small hardware overhead (2 spare (additional) 1K1 modules for each 1K16 of a memory system of 512K16, and Mean Time To Failure = 10−7 h−1). Finally, as we envisage a 2.4 μm CMOS implementation, we performed complexity estimations, which show that the supplementary self-tolerance ensuring circuitry involves an overhead of 0.0094% for a 512K16 memory. The recovering latency is minimised. For SEU in DRAM it requires zero latency and no more than the duration of an equivalent refresh cycle in SRAM. LU reflects a locality property, as only the affected module is submitted to the recovering algorithm. [ABSTRACT FROM AUTHOR]