Search

International audience; To meet the requirements of both costeffectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

International audience; Selecting the ideal trade-off between reliability improvement and cost (i.e., area, timing and power overhead) associated with a fault tolerant architecture generally requires an extensive Design Space Exploration. In this paper, we present a feasibility study that addresses the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Four different selective hardening methods have been investigated and compared: i) a full duplication scheme, ii) a reduced duplication scheme based on a structural susceptibility analysis, iii) a reduced duplication scheme based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication scheme that uses an approximate version of the arithmetic circuit. Experimental results performed on adder and multiplier case studies demonstrate the interest of using approximate structures in a duplication scheme since they provide much better error detection capability than other selective hardening methods with lower area and power overheads. Note that all experiments have been done without considering the area and power overhead due to the comparators. This may slightly biased the results from a quantitative point of view, although it does not jeopardize the main conclusion about the interest of using approximate structures as duplication scheme. Moreover, validations using a gate-level fault injection campaign have shown that approximate structures offer a better reliability level compared to the other considered duplication scenarios.

International audience; The outsourcing business model is dominating the semiconductor industry. Due to this loss of control over the design flow, several threats have become a major source of concern, including overproduction and IP overuse. For over a decade, several solutions have been proposed in the literature to counteract such threats. These solutions consist in hiding the behavior of the IPs/ICs until the design house securely unlocks them. This way, only unlocked IPs/ICs can be used properly while locked ones produce erroneous data. In this paper, we survey logic locking approaches and discuss locking quality in hiding expected behavior and in resisting to attacks.

International audience; Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to address this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technologies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect.

International audience; This paper addresses the problem of calibrating magnetically-coupled passive sensors for medical applications. We developed an analytical model of such sensor including the impact of some disturbances (distance and angle between antennas). This model is valid for sensors with different dimensions of antennas. Thanks to this model, the ideal indicator of the disturbances for calibration can be identified. It has been applied to the case study of Intra-Ocular Pressure (IOP) sensor. A new indicator (the slope of the baseline of the Bode phase plot) has been chosen.This new indicator is reliable to significant distance and angle variations between primary and secondary.

International audience; Increasing vulnerability of transistors and interconnects due to scaling is continuously challenging the reliability of future microprocessors. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this work we present a low-power hybrid fault tolerant architecture for reliability improvement of pipelined microprocessors by protecting their combinational logic parts. The architecture can handle a broad spectrum of faults with little impact on performance by combining different types of redundancies. Moreover, it addresses the problem of error propagation in nonlinear pipelines and error detection in pipeline stages with memory interfaces. Our case-study implementation of a fault tolerant MIPS microprocessor highlights four main advantages of the proposed solution. It offers (i) 11.6 % power saving, (ii) improved transient error detection capability, (iii) lifetime reliability improvement, and (iv) more effective fault accumulation effect handling, in comparison with TMR architectures. We also present a gate-level fault-injection framework that offers high fidelity to model physical defects and transient faults.

International audience; The diagnosis is the process of isolating possible sources of observed failures in a defective circuit. Today, manufacturing defects appear not only in the cell interconnection, but also inside the cell itself (intra-cell defect). State of the art diagnosis approaches can identify the defect location at gate level (i.e., one or more standard cells and/or inter-connections can be provided as possible defect location). Some approaches have been developed to target the intra-cell defects. In this paper, we propose an intra-cell diagnosis method based on the ``Effect-Cause'' paradigm aiming at locating the root cause of the observed failures inside a logic cell. It is based on the Critical Path Tracing (CPT) here applied at transistor level. The main characteristic of our approach is that it exploits the analysis of the faulty behavior induced by the actual defect. In other word, we locate the defect by simply analyzing the effect induced by the defect itself. The advantage is the fact that we are defect independent (i.e., we do not have to explicitly consider the type and the size of the defect). Moreover, since the complexity of a single cell in terms of transistor number is low, the proposed intra-cell diagnosis approach requires a negligible computational time. The efficiency of the proposed approach has been evaluated by means of experimental results carried out on both simulations-based and industrial silicon data case studies.

International audience; We present a study on the effects of resistive-bridging defects in the SRAM core-cell, considering different industrial technology nodes: 90 nm, 65 nm and 40 nm. We have performed an extensive number of electrical simulations, varying the resistance value of the defects, the supply voltage, the memory size and the temperature. We identified the worst-case conditions maximizing failure occurrence in presence of defects. Results also show that resistive-bridging defects cause malfunction in the defective core-cell, as well as in non-defective core-cells located in the same row and/or column. Moreover, the weak read fault is the fault that is the most likely to occur due to resistive-bridging defects. Finally, the sensitivity of SRAMs to resistive-bridging defects increases with the advance of technology nodes.

The test of analog & RF circuits at wafer-level suffers from both quality and throughput limitations, especially due to probing issues and limited count of expensive instrumentation resources. Since final test after packaging guarantees product performances, constraints on wafer-level test can be relaxed. This paper investigates a signal acquisition protocol based on the use of digital tester channels to perform the demodulation of analog/RF signals. Due to the large availability of such hardware resources on most testers, this approach allows to setup a multi-site strategy, thus increasing the test throughput. The fundamental concept is to capture the signal through the 1-bit comparator available in a digital tester channel and to process the resulting bit stream to retrieve the analog/RF signal characteristics. In this paper, the proposed solution is illustrated for the demodulation of Frequency-Modulated (FM) and Amplitude-Modulated (AM) signals. Both simulation and experimental results obtained with a Verigy 93K platform are presented.

International audience; This paper presents an on-line self-test architecture for hardware implementation of the Advanced Encryption Standard (AES). The solution exploits the inherent spatial replications of a parallel architecture for implementing functional redundancy at low cost. We show that the solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, the architectural modification for on-line test does not weaken the device with respect to side-channel attacks based on power analysis.

International audience; The design of secure ICs requires fulfilling means conforming to many design rules in order to protect access to secret data. On the other hand, designers of secure chips cannot neglect the testability of their chip since high quality production testing is primordial to a good level of security. However, security requirements may be in conflict with test needs and testability improvement techniques that increase both observability and controllability. In this paper, we propose to merge security and testability requirements in a control-oriented design for security scan technique. The proposed security scan design methodology induces an adaptation of two main aspects of testability technique design: protection at protocol level and at scan path level. Without loss of generality, the proposed solution is evaluated on a simple crypto chip in terms of security and design cost.

International audience; This paper presents a comparative analysis of ADOFs (Address Decoder Open Faults) and resistive-ADOFs in embedded-SRAMs. Such faults are the primary target of this study because they are hard-to-detect faults. These faults are caused by some particular defects which may appear in the parallel transistor network of the logic gates in the address decoders. With this study, we show that the test conditions required for ADOFs testing (sensitization and observation) are also useful for resistive-ADOFs detection, but more stringent timing requirements are needed. In the last part of the paper, we propose a study on the conditions to detect ADOFs with March tests. Moreover, we propose new March elements, which are effective for ADOF testing, and which can be added to existing March tests.

International audience; This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults may appear as the consequence of resistive-open defects that appear more and more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.

The long and complex procedure to test ADCs constitutes an important issue in the context of mixed-signal testing. To lower the testing costs, we propose shorter but less selective test flows solely based on spectral analysis. This paper investigates the efficiency that can be achieved using this approach and studies the influence of the ADC specifications on the efficiency of the proposed dynamic-only test flows.

This paper presents the application of the oscillation test methodology as an alternative to test configurable analog blocks of Field Programmable Analog Arrays. The blocks of the device under test are first configured to behave as oscillators. Then, the output frequency and amplitude are observed to obtain the signature of the fault-free circuit. During test, this signature is compared to the actual output signal. Experimental results show the effectiveness of the method in detecting parametric and large deviation faults of the tested components.

International audience; This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 μm embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an FPGA, not only for the system functionality, but also for the system testing, while keeping the performance level required by current signal processing applications. This paper presents the new FPGA model, along with preliminary experimental results that clearly show the possible advantages at the system level of merging design and test in a reconfigurable device.