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This paper presents simulations predicting the feasibility of 9-nm wraparound quantum dot channel (QDC) field-effect transistors (FETs). In particular, II–VI lattice-matched layers which reduce the density of interface states, serving as top (tunnel gate), side, and bottom gate insulators, have been simulated. Quantum simulations show FET operation with voltage swing of ~0.2 V. Incorporation of cladded quantum dots, such as SiO x –Si and GeO x –Ge, under the gate tunnel oxide results in electrical transport in one or more quantum dot layers which form a quantum dot superlattice (QDSL). Long-channel QDC FETs have experimental multistate drain current (I D)–gate voltage (V G) and drain current (I D)–drain voltage (V D) characteristics, which can be attributed to the manifestation of extremely narrow energy minibands formed in the QDSL. An approach for modeling the multistate I D–V G characteristics is reported. The multistate characteristics of QDC FETs permit design of compact two-bit multivalued logic circuits.

Electron wavefunctions are switched spatially from one quantum well to another by varying the gate voltage Vg in spatial wavefunction-switched (SWS) field-effect transistors (FETs), which comprise two or more coupled quantum wells serving as the transport channel. This is shown for Si/SiGe and InGaAs/AlInAs quantum well systems. The presence of charge in a particular well or channel is used to encode four states 00, 01, 10, 11. This unique property is used for two-bit processing, resulting in compact two-bit static random-access memory devices. Experimental data including capacitance–voltage peaks in Si and InGaAs multiple quantum well SWS-FETs has verified the SWS phenomenon. Replacing quantum wells by an array of cladded quantum dots, forming a quantum dot superlattice (QDSL) layer, enhances the contrast and noise margin in SWS-FETs. This paper reports I–V and C–V characteristics for a fabricated twin-drain SWS-quantum dot channel (QDC) FET comprising four layers of self-assembled SiOx-Si quantum dots. SWS-QDC-FETs are shown to be scalable to ∼9 nm, and comprise four layers of cladded quantum dots with an array of 3 × 3 forming the channel.

This study shows the use of a high-κ ZnS/ZnMgS/ZnS heteroepitaxial tunneling layer in an InGaAs field-effect transistor. Experimental fabrication and simulation of this semiconductor structure show promise of reducing threshold voltage variation by replacing silicon and hafnium oxides as a gate insulator. The II–VI tunneling insulator is grown on an InGaAs substrate using ultraviolet-irradiated metalorganic vapor-phase epitaxy. GeO x -Ge cladded quantum dots are self-assembled to form the gate material. The gate consists of two self-assembled individually cladded quantum dot layers which allow multilogic behavior. Simulations calculated by solving the Schrodinger and Poisson equations self-consistently confirm experimental I D–V D characteristics and show the electron distribution in an inversion channel/quantum well under different gate voltage bias values.

We present design equations for error function (or “S-graded”) graded buffers for use in accommodating lattice mismatch of heteroepitaxial semiconductor devices. In an S-graded metamorphic buffer layer the composition and lattice mismatch profiles follow a normal cumulative distribution function. Minimum-energy calculations suggest that the S-graded profile may be beneficial for control of defect densities in lattice-mismatched devices because they have several characteristics which enhance the mobility and glide velocities of dislocations, thereby promoting long misfit segments with relatively few threading arms. First, there is a misfit-dislocation-free zone (MDFZ) adjacent to the interface, which avoids dislocation pinning defects associated with substrate defects. Second, there is another MDFZ near the surface, which reduces pinning interactions near the device layer which will be grown on top. Third, there is a large built-in strain in the top MDFZ, which enhances the glide of dislocations to sweep out threading arms. In this paper we present approximate design equations for the widths of the MDFZs, the built-in strain, and the peak misfit dislocation density for a general S-graded semiconductor with diamond or zincblende crystal structure and (001) orientation, and show that these design equations are in fair agreement with detailed numerical energy-minimization calculations for ZnSySe1−y/GaAs (001) heterostructures.

This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors (SWS FETs) with Ge quantum wells and ZnSSe barriers. A two-bit SRAM cell consists of two back-to-back connected four-channel SWS FETs, where each SWS FET serves as a quaternary inverter. This architecture results in a reduction of the field-effect transistor (FET) count by 75% and data interconnect density by 50%. The designed two-bit SRAM cell is simulated using Berkeley short-channel insulated-gate field-effect transistor equivalent-channel models (for 25-nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology. Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count. The concept of spatial wavefunction switching (SWS) in the FET structure has been verified experimentally for two- and four-well structures. Quantum simulations exhibiting SWS in four-well Ge SWS FET structures, using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator, are presented. These structures offer higher contrast than Si-SiGe SWS FETs.

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiOx-cladded Si or GeOx-cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO2. Simulations involving self-consistent solutions of the Poisson and Schrodinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.

This paper describes the use of II–VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeOx-cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II–VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrodinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiOx-cladded Si or GeOx-cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiOx-cladded Si and GeOx-cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO2 tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (ID–VG) shows four-state behavior with two intermediate states between the conventional ON and OFF states.

The design of lattice-mismatched semiconductor devices requires a predictive model for strains and threading dislocation densities. Previous work enabled modeling of uniform layers but not the threading dislocations in device structures with arbitrary compositional grading. In this work we present a kinetic model for lattice relaxation which includes misfit–threading dislocation interactions, which have not been considered in previous annihilation–coalescence models. Inclusion of these dislocation interactions makes the kinetic model applicable to compositionally graded structures, and we have applied it to ZnSe/GaAs (001) and ZnSySe1−y/GaAs (001) heterostructures. The results of the kinetic model are consistent with the observed threading dislocation behavior in ZnSe/GaAs (001) uniform layers, and for graded ZnSySe1−y/GaAs (001) heterostructures the kinetic model predicts that the threading dislocation density may be reduced by the inclusion of grading buffer layers employing compositional overshoot. This “dislocation compensation” effect is consistent with our high-resolution x-ray diffraction experimental results for graded ZnSySe1−y/GaAs (001) structures grown by photoassisted metalorganic vapor-phase epitaxy.

An indium gallium arsenide quantum-dot-gate field-effect transistor using Zn0.95Mg0.05S as the gate insulator is presented in this paper, showing three output states which can be used in multibit logic applications. The spatial wavefunction switching effect in this transistor has been investigated, and modeling simulations have shown supporting evidence that additional output states can be achieved in one transistor.

This paper presents characteristics of two fabricated Si quantum dot gate field-effect transistors, one with SiOx-cladded Si dots on silicon dioxide as the gate insulator, and another with the same quantum dots on lattice-matched high-κ ZnS-ZnMgS-ZnS as the gate insulator. Simulations show that the oxide thickness should be within 80 A to generate a third state in the transfer characteristic of the quantum dot gate field-effect transistor. In the practical device, the silicon dioxide thickness varies between 20 A and 40 A. In this work we use high-κ dielectric thickness around 75 A to 80 A, which is equivalent to 32 A to 35 A of silicon dioxide.

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeOx)-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.

This paper describes fabrication and modeling of quantum dot channel (QDC) field-effect transistors (FETs). A QDC-FET comprises an array of thin-barrier (~1 nm) cladded Si, Ge, or other quantum dots (3 nm to 4 nm) forming an n-channel on a p-Si layer/substrate between the source and drain regions. Experimental characteristics of fabricated QDC-FETs, consisting of two layers of cladded quantum dot arrays (e.g., SiO x -cladded Si dots and GeO x -cladded Ge dots) serving as the transport channel, are presented. Unlike conventional FETs, QDC-FET structures exhibit step-like I D–V G characteristics and discretely bunched I D–V D characteristics as a function of gate voltage. The transfer characteristics appear to be similar to those of single-electron transistors (SETs). However, QDC-FETs employ transport of many electrons and operate at room temperature. A one-dimensional Tsu–Esaki equation is used to simulate the quantum dot channel and explain the steps in the current–voltage behavior. In particular, the effect of the II–VI barrier layers on Ge dots is modeled. The QDC-FET channel is also modeled as having superlattice-like mini-energy bands whose bandwidth and separation are determined by the dot size, cladding thickness, and barrier height. For a given gate voltage (which determines the carrier concentration), carriers in the inversion channel are transported via mini-energy bands that line up with the Fermi level as the drain voltage V DS is changed, producing step-like multistate electrical characteristics. Formation of the quantum dot channel enables higher-mobility transport on very low-mobility substrates or thin films such as poly-Si. The channel mobility can be further enhanced by partially removing the oxide barrier layer and replacing it with lattice-matched II–VI gate insulator layers.

High-resolution x-ray diffraction is a valuable nondestructive tool for structural characterization of semiconductor heterostructures, and the diffraction profiles contain information on the depth profiles of strain, composition, and defect densities in device structures. Much of this information goes untapped because the lack of phase information prevents direct inversion of the diffraction profile. The current practice is to use dynamical simulations in conjunction with a curve-fitting procedure to indirectly extract the profiles of strain and composition. These dynamical simulations have been based on perfect, dislocation-free laminar crystals, rendering the analysis inapplicable to structures having dislocation densities greater than about 106 cm−2. In this work we present a dynamical model for Bragg x-ray diffraction in semiconductor device structures with nonuniform composition, strain, and dislocation density, which is based on the Takagi–Taupin equation for distorted crystals and accounts for the angular and strain broadening of dislocations. We show that the x-ray diffraction profiles from ZnS y Se1−y multilayers and superlattices are strongly affected by the depth distribution of the dislocation density as well as the composition, suggesting that it should be possible to extract the profiles of composition, strain, and dislocation density by the analysis of measured diffraction profiles.

We have conducted a theoretical study of the equilibrium strain and misfit dislocation density profiles for “S-graded” buffer layers of InxGa1−xAs on GaAs (001) substrates in which the compositional profile follows a normal cumulative distribution function. On the basis of this modeling work we show that the S-graded layer exhibits misfit dislocation-free regions near the substrate interface and the free surface (or device interface). The equilibrium peak misfit dislocation density as well as the thicknesses of the dislocation-free regions may be tailored by design of the compositional profile; this in turn should enable minimization of the density of electronically active threading dislocations at the top surface. S-graded buffer layers may therefore facilitate the achievement of metamorphic device structures with improved performance compared with similar structures having uniform or linearly graded buffers.

This paper presents fabrication and characterization of a quantum dot-based floating gate nonvolatile memory device with site-specific self-assembly of germanium oxide-cladded germanium (GeOx-Ge) quantum dots on SiO2 and ZnS/ZnMgS/ZnS (II–VI lattice-matched high-κ dielectric) tunnel insulator material. These monodispersed and individually cladded quantum dots have the potential to store charge uniformly in the floating gate and are well suited for nonvolatile memory applications.

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeOx-cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high-κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeOx-Ge quantum dots.

This paper presents the implementation of a novel InGaAs field-effect transistor (FET), using a ZnSe-ZnS-ZnMgS-ZnS stacked gate insulator, in a spatial wavefunction-switched (SWS) structural configuration. Unlike conventional FETs, SWS devices comprise two or more asymmetric coupled quantum wells (QWs). This feature enables carrier transfer vertically from one quantum well to another or laterally to the wells of adjacent SWS-FET devices by manipulation of the gate voltages (Vg). Observation of an extra peak (near both accumulation and inversion regions) in the capacitance–voltage data in an InGaAs-AlInAs two-quantum-well SWS structure is presented as evidence of spatial switching. The peaks are attributed to the appearance of carriers first in the lower well and subsequently their transfer to the upper well as the gate voltage is increased. The electrical characteristics of a fabricated SWS InGaAs FET are also presented along with simulations of capacitance–voltage (C–V) behavior, showing the effect of wavefunction switching between wells. Finally, logic operations involving simultaneous processing of multiple bits in a device, using coded spatial location of carriers in quantum well channels, are also described.

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap ZnyCd1−ySe-cladded ZnxCd1−xSe quantum dots (y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in ZnyCd1−ySe, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II–VI quantum dots as well as two diverse types of devices are presented in this paper.

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeOx-cladded Ge quantum dots as the charge storage units. A Si3N4 layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeOx-cladded Ge and SiOx-cladded Si quantum dots (QDs) are self-assembled site-specifically on the II–VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II–VI stack serves both as a tunnel insulator and a high-κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

Exponentially graded semiconductor layers are of interest for use as buffers in heteroepitaxial devices because of their tapered dislocation density and strain profiles. Here we have calculated the critical layer thickness for the onset of lattice relaxation in exponentially graded InxGa1−xAs/GaAs (001) heteroepitaxial layers. Upwardly convex grading with \( x = x_{\infty } \left( {1 - {\rm e}^{ - \gamma /y} } \right) \) was considered, where y is the distance from the GaAs interface, γ is a grading length constant, and x∞ is the limiting mole fraction of In. For these structures the critical layer thickness was determined by an energy-minimization approach and also by consideration of force balance on grown-in dislocations. The force balance calculations underestimate the critical layer thickness unless one accounts for the fact that the first misfit dislocations are introduced at a finite distance above the interface. The critical layer thickness determined by energy minimization, or by a detailed force balance model, is approximately \( h_{\rm{c}} \approx 0.243\;\mu {\hbox{m}}\left( {\gamma /1\;\mu {\hbox{m}}} \right)^{0.5} \left( {x_{\infty } /0.1} \right)^{ -0.54} . \) Although these results were developed for exponentially graded InxGa1−xAs/GaAs (001), they may be generalized to other material systems for application to the design of exponentially graded buffer layers in metamorphic device structures such as modulation-doped field-effect transistors and light-emitting diodes.

We report an experimental and modeling study of ZnS y Se1−y /GaAs (001) structures, all of which comprised a uniform top layer of ZnS0.014Se0.986 grown on a compositionally graded buffer layer or directly on the GaAs substrate. High-resolution x-ray diffraction was used to estimate dislocation densities on type A slip systems, with misfit dislocation (MD) line segments oriented along the $$ [1\bar{1}0] $$ direction, and type B slip systems, with MD line segments oriented along a [110] direction. A control sample having no graded buffer exhibits equal dislocation densities on the two types of slip systems (D A ≈ D B ≈ 1.5 × 108 cm−2), but a forward-graded (FG) structure (grading coefficient of 27 cm−1) exhibits 20% more dislocations on the type B slip systems (D A ≈ 1.6 × 108 cm−2 and D B ≈ 1.9 × 108 cm−2) and a steep forward-graded structure (grading coefficient of 54 cm−1) exhibits 50% more type B dislocations (D A ≈ 2 × 108 cm−2 and D B ≈ 3 × 108 cm−2). The insertion of an overshoot interface reduced the dislocation densities in the uniform top layer by promoting annihilation and coalescence reactions, but type B dislocations were removed more effectively. Based on equilibrium calculations the overshoot graded layer in the steep graded overshoot structure is expected to exhibit large compressive and tensile strains, with a reversal in the sign of the strain near its middle, which may promote annihilation and coalescence reactions between threading dislocations.

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

We have studied the use of overshoot graded layers for the control of the dislocation density in mismatched heteroepitaxial layers. Graded ZnS y Se1–y structures were grown on GaAs (001) by photoassisted metalorganic vapor-phase epitaxy (MOVPE) and characterized by high-resolution x-ray diffraction (HRXRD). All samples had a uniform top layer of ZnS0.014Se0.986, and various graded layers were incorporated between the substrate and the uniform top layer; these included forward-graded (FG) and reverse-graded (RG) buffers. Some structures incorporated overshoot at the interface with the uniform top layer (FGO and RGO buffers). Among the FG samples, those with overshoot exhibited better crystal quality and lower dislocation densities than those without. This is expected because the mismatched interface between the graded layer and the top ZnS0.014Se0.986 can affect the bending over of threading dislocations for the production of misfit dislocations, indirectly promoting annihilation and coalescence reactions. An overshoot interface with 0.1% mismatch was found to remove 2 × 108 cm−2 dislocations from the top device layer. Overshoot did not reduce the dislocation density in RG structures, but this may be because the sign of the overshoot caused the generation of new dislocations rather than interactions between existing ones. For growing a high-quality device layer with minimal defect density, it appears that steep forward-graded layers with overshoot may be best in this material system.