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In this study, a low-temperature co-fired ceramic (LTCC)-based direct current (DC)-DC converter is proposed for reducing stray inductance and mitigating electromagnetic interference. The dominant radiating loop of the proposed LTCC-based DC-DC converter features a multilayer design, which helps suppress noise sources and reduce radiated emissions. The peak voltage of switching noise for the proposed DC-DC converter at the frequency of 500 kHz is approximately 8.98% lower than that of a conventional DC-DC converter. In addition, the radiated emission level of the proposed DC-DC converter is lower than that of the conventional DC-DC converter. In sum, the proposed LTCC-technology-based multilayer design reduces the peak voltage of switching noise and the radiated emission of the DC-DC converter.

In this paper, using the 0.2 μm ETRI GaN HEMT process, we developed a C-band GaN dual-feedback low-noise amplifier MMIC for an RF receiver module that requires high-input power robustness. By applying a feedback microstrip line at the source of the transistor and series resistor-capacitor (RC) feedback between the gate and the drain of the transistor, we obtained stable amplifier operation and a compromised impedance trace for both input impedance matching and noise matching while suppressing performance degradation of the maximum available gain and minimum noise figure. The developed low-noise amplifier MMIC, which implements simple matching circuits by using biasing elements as matching elements, had a linear gain of more than 21.4 dB and a noise figure of less than 1.91 dB in the wide bandwidth of 4.3–7.4 GHz. Under the single-tone power test, the low-noise amplifier MMIC had an output P1dB of 14.3–20.1 dBm, and the two-tone intermodulation distortion measurement exhibited an input third-order intercept point (IIP3) of 2.2–5.6 dBm in the same frequency range as the above.

This letter introduces a power limiter that limits the input power to protect the receiver when a large power enters the radio frequency receiver. When the power limiter receives a large power signal, a positive-intrinsic-negative (PIN) diode is turned on to limit the input power by lowering the impedance. We analyzed the characteristics of the power limiter according to the method of connecting the PIN diode in parallel with the input and output transmission lines of the power limiter. By embedding a PIN diode into the cavity and minimizing the length of the wire, a power limiter was designed and implemented to minimize parasitic inductance. In the S-band, the proposed power limiter’s insertion loss was below 0.5 dB, and the reflection loss characteristics were below 15 dB. Furthermore, it achieved an output P1dB of 21.8 dBm at 3.5 GHz.