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A significant amount of processor power is required to handle packet processing in high speed data networks and taking it to the hardware helps processor to save its energy for other processes. In this study, an Offload Engine IP core that provides the hardware acceleration of UDP/IP protocol stack together with a few other network protocols is introduced. Furthermore, the IP core is equipped with PCI Express (PCIe) interface so as to communicate with applications running on a host PC. Consequently, a processor core deals with only the data processing, while the IP core takes care of the packet processing as per the protocol. The design and implementation of the IP core are verified and tested on an FPGA board; its area utilization and supported features are compared against several competitive designs from the literature. According to these results, the IP core is proved to be a useful one for those network applications that require a hardware-accelerated network protocol stack. [ABSTRACT FROM AUTHOR]

Random numbers are highly used in applications like computer simulation, gambling, statistical sampling and cryptography. Only a high-entropy random source can produce a better quality of random data. In this paper, we work on the generation of high-quality random numbers based on cellular automata (CA). We propose three-dimensional (3D) CA to generate a random sequence. We also propose various enhancements to CA-based pseudorandom number generator (CA-PRNG) and discuss its five variants by using two-dimensional (2D) and 3D CA. We analyze the switching between 2D and 3D CA for the same sequence to achieve high-quality randomness. We provide the architectures, CA rules and the algorithms for all the proposed variants with respect to 2D and 3D cell structures. We have done a software implementation of all the proposed variants and tested their produced sequences by using the internationally accepted standard for random numbers known as DIEHARD. The analysis of our results is made as per the recommendations of ANSI standards. A very similar criteria are applied to compare all the methods. Based on our results we are able to find the best CA-PRNG for producing high-quality random sequence. [ABSTRACT FROM AUTHOR]

This paper proposes universal coarse-grained reconfigurable computing architecture for hardware implementation of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs), suitable for both field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs) implementation. Using this universal architecture, two versions of DTs (functional DT and axis-parallel DT), two versions of SVMs (with polynomial and radial kernel) and two versions of ANNs (multi layer perceptron ANN and radial basis ANN) machine learning classifiers, have been implemented in FPGA. Experimental results, based on 18 benchmark datasets of standard UCI machine learning repository database, show that FPGA implementation provides significant improvement (1-2 orders of magnitude) in the average instance classification time, in comparison with software implementations based on R project. [ABSTRACT FROM AUTHOR]

Steganography has become an important method for concealed communication especially through image files. Recent proposed steganographic methods employ multiple levels of complex techniques. Hence, there is an increasing significance for hardware implementation and its performance metrics. The objective of this article is to analyze and model the performance of FPGA hardware implementations of several spatial steganography methods, including: least significant bit (LSB), random LSB, mix-bit LSB and texture method. This paper presents innovative models to estimate energy-to-embed-secret-bit, peak signal-to-noise-ratio (PSNR) energy cost, power and resources in complex systems. Examining the performance results of the FPGA implementations shows that embedding misalignment degrades the performance, and random embedding increases resources by 43% and power by 13%. Furthermore, the mix-bit method has the best results in terms of balancing the energy consumption and PSNR. Moreover, the accuracy of the model to predict the energy to embed a single secret bit is 2%, and the accuracy of the model to predict complex system performance is 1% for hardware resources and 16.6% for power. [ABSTRACT FROM AUTHOR]

Modular exponentiation is a basic operation in cryptosystems. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. The efficiency of the modular exponentiation, in turn, depends mainly on that of modular multiplications as the former is somehow a repetition of the latter. One of the methods that computes the modular power is the sliding-window method, which pre-processes the exponent into zero and nonzero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel System-on-Chip (SoC) implementation for computing modular exponentiation using the sliding-window method. We also propose a hardware-only implementation for that operation. The partitioning strategy used in both approaches allows constant-length nonzero partitions, which increases the average number of zero partitions and so decreases that of nonzero partitions. The partitioning strategy allows variable-length zero partitions. The hardware/software co-design implements the modular multiplication on hardware and the rest of the system in software. We provide a useful comparison of the SoC-based implementation against hardware-only implementation. Both of the proposed implementations can be used in any industrial embedded system that needs to secure the handled information. [ABSTRACT FROM AUTHOR]

Reconfigurable Systems represent a middle trade-off between speed and flexibility in the processor design world. It provides performance close to the custom-hardware and yet preserves some of the general-purpose processor flexibility. Recently, the area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse-grain hardware. Since the field is still in its developing stage, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndael and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. We present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology we used can be utilized in other systems. [ABSTRACT FROM AUTHOR]