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We investigate the MX2 (M = {Hf, Zr}, X = {S, Se}) transition metal dichalcogenides patterned into armchair (AC) and zigzag (ZZ) nanoribbons (NRs) as potential channel materials in future logic field-effect devices. Ab initio quantum transport simulations are employed to assess the electronic, transport, and ballistic field-effect transistor (FET) properties of devices with such quasi-one-dimensional channels. We report a non-monotonic scaling behavior of MX2NR properties due to strong quantum confinement effects, which is reflected in a strong dependence of the ON-state current (ION) of MX2NR FETs on the nanoribbon configuration. The ∼2 nm-wide HfSe2 and ZrSe2 AC-PFETs have the highest ION of up to 2.6 mA/μm at 10 nA/μm OFF-state current. Surprisingly, MX2NR ZZ-NFETs exhibit a current increase of up to 70% when channel width is scaled down, with ION reaching 2.2 mA/μm in ∼2 nm-wide devices. The high ON-state performance is a direct consequence of high carrier injection velocity, which is explained by analyzing the band structure, transmission, and density of states. We demonstrate that nanostructured MX2 materials can be promising candidates for future logic transistors based on multi-nanowire architectures. [ABSTRACT FROM AUTHOR]

The deep-level drain current transient spectroscopy (Id-DLTS) measurements of Al -doped SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) strongly suggest that the reduction in the channel mobility at low temperatures is related to a shallow trap detectable at 70 K. Using the Shockley–Reed–Hall (SRH) theory, the level of this trap has been extracted to be around 0.15 eV below the conduction band minimum of SiC. Density functional theory (DFT) calculations of Al Si N C Al Si and Al Si O C Al Si defect complexes have found one configuration of the Al Si O C Al Si complex, which has a charge transition level within the SRH extracted trap level range. Therefore, we suggest that these Al Si O C Al Si defects are likely candidates for traps responsible for the channel mobility reduction. [ABSTRACT FROM AUTHOR]

Large Schottky barriers formed at the interfaces between graphene and 2D semiconductors often degrade device performance. Here, taking the Janus MoSO as a prototype and using the first-principles calculations together with the band unfolding technique, we demonstrate that the Ohmic contact (OC), which is absent in pristine graphene/MoXY (X/Y = S, Se, Te. X ≠ Y), is realized in the pristine graphene/MoSO (G/MoSO) heterostructure. G/OMoS shows the n -type OC (OC- n) that leads to the p -doping of the graphene layer with a hole density of 1.17 × 10 13 /cm 2 , while G/SMoO exhibits the p -type Schottky contact with a tunable Schottky barrier height. The realization of OC and the interface dependent contact type are mainly attributed to the large intrinsic dipole between asymmetric S and O layers, which dominate the different behaviors of charge transfer and the associated interface dipole in heterostructures. Inspired by the finding, considering the larger dipole moment in Janus MoSeO and MoTeO, we further confirm that both OC- n and OC- p exist in pristine G/MoSeO and G/MoTeO. Moreover, on comparison with MoSO, both G/OMoS and G/SMoO show enhanced optical absorptions (∼ 10 5 cm − 1 ) in most of the visible light range. Our results not only show the potential application of G/MoSO in nanoelectronic devices such as field-effect transistors but also indicate that dipole engineering would help us to predict or design desirable electric contacts of Janus-transition metal dichalcogenide-based metal/semiconductor systems in advance. [ABSTRACT FROM AUTHOR]

The successful synthesis and discovery of unique properties in two-dimensional Janus materials have positioned them as promising candidates for applications in sensors, field-effect transistors, and ultrasensitive detectors. In this study, we utilized first-principles calculations to predict a novel Janus CeIBr monolayer. Our calculations show that Janus CeIBr monolayer behaves as a bipolar magnetic semiconductor, demonstrating both mechanical and thermodynamic stability, along with a high Curie temperature of 242 K and in-plane magnetic anisotropy (102.92 meV). A notable intrinsic valley splitting of 66 meV is also evident in CeIBr, highlighting its distinctive valley contrast characteristic. Furthermore, the application of biaxial strain effectively transforms the magnetic ground state of CeIBr from a ferromagnetic state to an antiferromagnetic state and alters the direction of the easy magnetization axis from in-plane to out-of-plane. Our findings offer a theoretical foundation for the design of novel anomalous valley Hall effect-based electronic devices utilizing the Janus CeIBr monolayer. [ABSTRACT FROM AUTHOR]

4H-SiC/ SiO 2 interface states play a major role in the performance and reliability of modern 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs). To gain new insights into these interface states, we developed a cryogenic measurement technique that uses photon-assisted electron depopulation to probe device performance limiting 4H-SiC/ SiO 2 interface states. This technique enables the characterization of shallow as well as deep states at the 4H-SiC/ SiO 2 interface of fully processed devices using a cryogenic probe station. Our method is performed on n-channel 4H-SiC MOSFET test structures with deposited oxide and postoxidation anneal. We identify conditions under which the electrons remain trapped at 4H-SiC/ SiO 2 interface states and trigger the controlled photon-assisted electron depopulation within a range of photon energies. This allows us to prove the presence of near interface traps, which have previously been found in thermally grown 4H-SiC MOS structures. Our results are supported by device simulations. Additionally, we study the impact of irradiation intensity and light exposure time on the photon-induced processes. [ABSTRACT FROM AUTHOR]

We propose a main mechanism of large valley splitting experimentally observed at the interface of buried oxide (BOX)/silicon-on-insulator (SOI) structures. Silicon metal-oxide-semiconductor field effect transistors fabricated on a SIMOX (001) substrate, which is a kind of the SOI substrate, that is annealed at high temperatures for a long time are known to exhibit large valley splitting, but the origin of this splitting has long been unknown. Extended zone effective-mass approximation predicts that strain significantly affects valley splitting. In this study, we analyzed valley splitting based on this theory and found that the shear strain along [110] of approximately 5% near the BOX interface is a promising source for large valley splitting. [ABSTRACT FROM AUTHOR]

The ultra-wide bandgap of gallium oxide provides a rich plethora of electrically active defects. Understanding and controlling such defects is of crucial importance in mature device processing. Deep-level transient spectroscopy is one of the most sensitive techniques for measuring electrically active defects in semiconductors and, hence, a key technique for progress toward gallium oxide-based components, including Schottky barrier diodes and field-effect transistors. However, deep-level transient spectroscopy does not provide chemical or configurational information about the defect signature and must, therefore, be combined with other experimental techniques or theoretical modeling to gain a deeper understanding of the defect physics. Here, we discuss the current status regarding the identification of electrically active defects in beta-phase gallium oxide, as observed by deep-level transient spectroscopy and supported by first-principles defect calculations based on the density functional theory. We also discuss the coordinated use of the experiment and theory as a powerful approach for studying electrically active defects and highlight some of the interesting but challenging issues related to the characterization and control of defects in this fascinating material. [ABSTRACT FROM AUTHOR]

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

The rising temperature due to a self-heating or thermal environment not only degrades the subthreshold performance but also intensifies thermal stress, posing a severe challenge to device performance and reliability design. The thermal stress effects on the ON-state performance of the p-type fin field-effect transistor were previously studied. However, as far as we know, how thermal stress affects its subthreshold conduction remains unclear, which is studied in this manuscript. The impact of thermal stress due to the self-heating of adjacent devices on subthreshold conduction is investigated by solving the quantum transport, thermal conduction, and force balance equations for ballistic transport and dissipative transport with phonon scattering. Then, the thermal stress effects at different ambient temperatures are further discussed and analyzed. The simulation results show that the OFF-state leakage current can be reduced by thermal stress, even up to 9.28% for the (110)/[001] device operating at an ambient temperature of 550 K, and its reduction is the comprehensive result of the thermal stress effects on the band structure, potential profile, carrier distribution, and source-to-drain tunneling. In addition, the thermal stress has no significant effects on subthreshold swing although it can change the magnitude of the subthreshold current. Moreover, the effect of thermal stress on subthreshold conduction is highly dependent on the thermal environment of the device and the crystal orientation of the channel semiconductor material. [ABSTRACT FROM AUTHOR]

The performance of SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) degrades seriously after a period of continuous operation. To directly understand this issue, we conduct real-time time-dependent density functional theory (TDDFT) simulations on a series of nitrogen passivated SiC– SiO 2 interfaces to monitor the interaction between carriers and interface atoms. We find that the nitrogen passivation always leaves behind two local states near the VBM, which gives a chance to the strong interaction between channel carriers and C–N bonds, and finally results in the generation of C dangling bond defects. These processes are vividly presented and confirmed by the TDDFT simulation. Additionally, the results show that the new defects are more easily formed by the passivated C cluster than the passivated Si vacancy. These studies provide physical insights into the degradation mechanisms of working SiC MOSFETs, while simultaneously demonstrating the advantage of TDDFT as a crucial tool for investigating defect generation dynamics in semiconductor devices. [ABSTRACT FROM AUTHOR]

Gallenene is a novel metallic 2D material that can provide a semiconducting counterpart if patterned into quasi-one-dimensional (quasi-1D) nanostructures, i.e., gallenene nanoribbons (GaNRs). We investigate semiconducting GaNRs as a potential channel material for future ultrascaled field-effect transistors (FETs) by employing quantum transport simulations based on Green's functions and tight-binding Hamiltonians with the orbital resolution calibrated on ab initio calculations. The impact of GaNR width downscaling from ∼6 nm down to ∼0.2 nm on the electronic, transport, and ballistic device properties is investigated for the FET channel length of 15 nm. We report current enhancement and injection velocity overshoot effects for sub-1.2 nm-wide nFETs and pFETs, with a maximum current increase of 53% in the 1.2 nm-wide GaNR pFET in comparison to the widest device. In addition, promising current-driving capabilities of n- and p-channel GaNR FETs are observed with top ballistic currents of more than 2.2 mA/μm and injection velocities of up to 2.4 × 107 cm/s. The reported data are explained by analyzing the evolution of band structure and related parameters such as injection velocity, quantum capacitance, effective transport mass etc., with increasing quantum confinement effects in ultranarrow GaNRs. Generally, we find that quasi-1D gallenene is a promising channel material for future nanoscale FETs, especially for transistor architectures based on stacked nanosheets. [ABSTRACT FROM AUTHOR]

Negative differential resistance (NDR) is observed in various emerging electronic devices. As compared to the conventional silicon-based field effect transistor (FET), the NDR is widely investigated in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs. In this work, we study the NDR effect for the TMD-based metal-edge-contact MoS 2 double-gate FET with 10 nm channel length. The multiscale atomistic simulation is demonstrated for the lateral heterostructure of a metal–semiconductor–metal FET by density functional theory, maximally localized Wannier function tight-binding Hamiltonian, and non-equilibrium Green's function methods. The quantum transport model in the given lateral heterostructure resulted in NDR in a double-gate FET. Here, we focus on the NDR by the systematic study of the transmission spectrum of the metal-edge-contact MoS 2 channel FET and finally compare it with zero NDR ideal highly doped FET. The peak-to-valley ratio in the NDR response can be modulated with the change in the gate-to-source voltage and can be used to explore various future electronic applications. [ABSTRACT FROM AUTHOR]

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices. [ABSTRACT FROM AUTHOR]

Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process. [ABSTRACT FROM AUTHOR]

For over half a century, traditional silicon-based integrated circuits (ICs) have been the basis of computational electronics and are widely used in computers, cell phones, and other fields. With the rapid development of human society, silicon-based semiconductor technology is approaching its physical and engineering limits. Our increasing diversity of non-traditional computing needs, such as ultra-small, ultra-fast, ultra-low-power wearables, and space radiation protection, is driving the search for new electronic materials. Semiconducting single-walled carbon nanotubes (s-SWCNTs) have many excellent electrical properties, such as high carrier mobility and high ballistic transport, making them strong candidates for new semiconductor materials in the post-Moore era. Carbon-based electronic technology has been developed for over 20 years, and the fundamental issues such as the material purification of s-SWCNTs, preparation prospects of s-SWCNT-based field-effect transistors (CNT FETs), and device physics based on CNT FETs have been basically solved. However, the chiral diversity of s-SWCNTs may lead to problems such as fluctuations in the electrical performance of CNT FETs, limiting the application of s-SWCNTs in high-end ICs. Monochiral s-SWCNTs not only have excellent electrical properties but also have a controllable structure and uniformity, which are crucial for the high-end IC of CNTs. However, some problems exist in the purity and yield of monochiral s-SWCNT preparation and the optimization of monochiral CNT FETs. Therefore, the chiral sorting of CNTs is reviewed in this paper, and the progress of polymer reprocessing in chiral separation is highlighted. Then, the research progress of monochiral CNT FETs is introduced, and possible development directions are summarized and analyzed. Finally, the application prospects of chiral-enriched s-SWCNTs include challenges and future opportunities. [ABSTRACT FROM AUTHOR]

Theoretical models have predicted that pH-responsive surface groups can reduce the sensitivity of field-effect transistor biosensors. However, attempts to prove this experimentally have shown conflicting results. In this work, a graphene field effect transistor (gFET) biosensor is used, which, without modification, is pH insensitive. The surface of the graphene is then functionalized using 1-hydroxypyrene to modulate the pH sensitivity of the gFET. A pH sensitivity ranging from 3.9 to 36.8 mV/pH was demonstrated. The biosensitivity of the gFETs was tested using streptavidin–biotin as a model system. The experimental results showed no correlation between biosensitivity and pH sensitivity. An electrochemical membrane model was used to determine the expected relationship between biosensitivity and pH sensitivity. The model results show that biosensitivity does not decrease until a certain threshold pH sensitivity is reached. This threshold is dependent on factors such as the acid dissociation constants of the surface hydroxyl groups and ion concentration. Furthermore, the differences between the simulation and experiment suggest that the effect of screening is greatly reduced when the analyte binds within a membrane. [ABSTRACT FROM AUTHOR]

In this study, the ungated AlGaN/GaN devices with special mesa structures were designed. The hypothesis of effective width expansion was tested experimentally by using ungated samples with different sizes, and an empirical expression for calculating the conduction channel effective width was given according to the experimental results. Finally, split-gate AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate lengths were prepared, and the channel electron mobility of split-gate samples was calculated by using the empirical expression and polarization Coulomb field (PCF) scattering theoretical model. The results showed that, for split-gate AlGaN/GaN HFETs, with the increase in the gate length, the total amount of additional polarization charges underneath the gate increases, resulting in the enhancement of the PCF scattering intensity. [ABSTRACT FROM AUTHOR]

This paper investigates near-interfacial charge trapping effects in graphene field-effect transistors with high-K gate dielectrics. Experimental and model-based analysis elucidates the impact of trapped charge on the transport properties of graphene. Landauer formalism is applied to correlate trapping-enhanced charged impurity scattering to degradation in conductivity and mobility. The analysis shows a significant reduction in conductivity and mobility with a transition toward the dominance of charge impurity scattering as evidenced by their dependence on the sheet carrier density. Moreover, we quantify the impact of trapped charge buildup on the carrier backscattering mean free path associated with charged impurities. This work provides new insights into the impact of charge trapping toward the development of logic, memory, and neuromorphic devices based on graphene and other low-dimensional materials and ultrascaled high-K dielectrics. [ABSTRACT FROM AUTHOR]

Graphene-based field-effect transistors (FETs) are suitable for pH sensors due to their outstanding surface chemical properties and its biocompatibility. To improve the devices' stability and pH sensitivity, different sets of dielectric passivation layers composed of monolayer hexagonal boron nitride with and without aluminum oxide layers were evaluated. Non-linearities of the pH response were observed. Heterostructure FETs were derived from subtractive manufacturing of commercially transferred two-dimensional materials on four-inch SiO2/Si wafers via stainless steel and polypropylene masking. Phosphate solutions (10 mM) of varying pH were incubated on bare devices, whereby liquid-gating elucidated linear changes in the Dirac voltage of hBN/graphene (−40 mV/pH) that was smaller than a device consisting only of monolayer graphene (−47 mV/pH). Graphene-based FETs were passivated with aluminum oxide nanofilms via electron beam or atomic layer deposition and were observed to have distinct Raman spectral properties and atomic force microscopy topologies corroborating the hypothesis that morphological differences of the deposited aluminum oxide influence the pH-dependent electrical properties. Atomic layer deposition of aluminum oxide on the 2D sensing areas resulted in non-linear shifting of the Dirac voltage with respect to pH that evolved as a function of deposition thickness and was distinct between graphene with and without hexagonal boron nitride as a capping monolayer. The non-linear response of varying thickness of AlxOy on graphene-based FETs was progressively reduced upon basic wet etching of the AlxOy. Overall, passivated graphene-based transistors exhibit deposition-dependent pH responses. [ABSTRACT FROM AUTHOR]

We propose and analyze the performance of terahertz (THz) room-temperature bolometric detectors based on the graphene channel field-effect transistors (GC-FET). These detectors comprise the gate barrier layer (BL) composed of the lateral hexagonal-boron nitride black-phosphorus/hexagonal-boron nitride (h-BN/b-P/h-BN) structure. The main part of the GC is encapsulated in h-BN, whereas a short section of the GC is sandwiched between the b-P gate BL and the h-BN bottom layer. The b-P gate BL serves as the window for the electron thermionic current from the GC. The electron mobility in the GC section encapsulated in h-BN can be fairly large. This might enable a strong resonant plasmonic response of the GC-FET detectors despite relatively lower electron mobility in the GC section covered by the b-P window BL. The narrow b-P window diminishes the Peltier cooling and enhances the detector performance. The proposed device structure and its operation principle promote elevated-temperature GC-FET THz detector responsivity values and other characteristics, especially at the plasmonic resonances. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) power devices are becoming central components in high voltage electronics. However, defects at interfaces and in the bulk continue to severely impact their reliability and performance. Here, we develop a charge pumping method to characterize SiC/SiO 2 interface defects in fully fabricated commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The method is then used to address spin states at the SiC/SiO 2 interface via charge pumping electrically detected magnetic resonance (CP-EDMR). We apply these methods to investigate the power MOSFET after electron irradiation over a dose range of 10 13 − 10 17 cm − 2 . We finally discuss CP-EDMR as a technique to interrogate spins during device operation for real-time monitoring of the device quality, performance, and degradation and as a probe for local magnetic fields. [ABSTRACT FROM AUTHOR]

Switching a silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor between inversion and accumulation with removed drain and grounded source terminals leads to defect-assisted carrier recombination and light emission. The energy spectrum of the emitted photons provides valuable information on the involved defects, located both at the 4H-SiC/ SiO 2 interface and in the 4H-SiC bulk. Here, we measured and analyzed the emitted light over a broad temperature range between 12 and 297 K. Our results reveal two local maxima in light intensity around 30 and 140 K. Most importantly, the local intensity maxima and the related temperatures correlate with both the overall recombination current and gate capacitance measurements. The spectral analysis allowed us to distinguish between recombinations occurring on 4H-SiC bulk defects and 4H-SiC/ SiO 2 interface-related defects. We explain an initial increase of light emission with decreasing temperature to competing non-radiative pathways with activation energies of 34 and 60 meV for SiC/ SiO 2 interface- and 4H-SiC bulk-related emissions, respectively. Based on an extensive literature review, we link the measured photon emission to donor–acceptor pair recombination, the EH 6 / 7 or the Z 1 / 2 defect centers. In addition to that, we could link a prominent peak at 2.915 eV to the L 1 line of the D 1 -center. Most importantly, we conducted our own ab initio simulations revealing that recombination via P bC -centers, previously identified with carbon dangling bonds at the 4H-SiC/ SiO 2 interface [Cottom et al., J. Appl. Phys. 124, 045302 (2018)], could also provide an explanation for the photon emission around 1.75 eV. Finally, our simulation of an interface-related silicon vacancy V Si , I reveals a radiative transition around 2.8 eV. [ABSTRACT FROM AUTHOR]

In this work, we study the electronic properties of nanotubes with spin–orbit interaction that exhibit a spin Hall effect. Nanoribbons made of these materials are expected to have topologically protected states. The lack of edge states in a seamless tube eliminates the possibility of finding a topological edge state. The spin–orbit interaction breaks the degeneracy of Dirac's cones and eliminates the chance of finding a metal nanotube. As a consequence, this makes all nanotubes with spin–orbit interaction trivial band insulators. We focus our attention on two features. First, we study the energy band gap as a function of the diameter of the nanotubes. Then, we concentrate on controlling the bandgap of a nanotube by applying an external radial electric field. Finally, we discuss the possibility of using one of these tubes as a field-effect transistor. [ABSTRACT FROM AUTHOR]

We evaluate the terahertz (THz) detectors based on field-effect transistor (FET) with the graphene channel (GC) and a floating metal gate (MG) separated from the GC by a black-phosphorus (b-P) or black-arsenic (b-As) barrier layer. The operation of these GC-FETs is associated with the heating of the two-dimensional electron gas in the GC by impinging THz radiation leading to thermionic emission of the hot electrons from the GC to the MG. This results in the variation of the floating gate potential, which affects the source–drain current. At the THz radiation frequencies close to the plasmonic resonance frequencies in the gated GC, the variation of the source–drain current and, hence, the detector responsivity can be resonantly large. [ABSTRACT FROM AUTHOR]

Epitaxial graphene (EG) on cubic silicon carbide (3C-SiC) on silicon holds the promise of tunable nanoelectronic and nanophotonic devices, some uniquely unlocked by the graphene/cubic silicon carbide combination, directly integrated with the current well-established silicon technologies. Yet, the development of graphene field-effect devices based on the 3C-SiC/Si substrate system has been historically hindered by poor graphene quality and coverage, as well as substantial leakage issues of the heteroepitaxial system. We address these issues by growing EG on 3C-SiC on highly resistive silicon substrates using an alloy-mediated approach. In this work, we demonstrate a field-effect transistor based on EG/3C-SiC/Si with gate leakage current 6 orders of magnitude lower than the drain current at room temperature, which is a vast improvement on the current literature, opening the possibility for dynamically tunable nanoelectronic and nanophotonic devices on silicon at the wafer level. [ABSTRACT FROM AUTHOR]

The ferroelectric field effect transistor (FeFET) is a very promising candidate for low-power and non-volatile memory. However, the co-existing effect of ferroelectric polarization and interface charge trapping in the FeFETs is demonstrated and many efforts have been made to eliminate this charge-trapping effect, which is usually treated as a deleterious effect. In contrast, we have found that the charge-trapping effect can play a dominant role in ferroelectric gates. In this work, we have verified that the charge-trapping effect of the ferroelectric/insulator interface could induce a memory window as the main physical mechanism in the TiN/Hf0.5Zr0.5O2/SiO2/p-Si (MFIS) structure, in which the ferroelectric characteristics of HZO thin films was verified through a reverse-grown MFIS structure. We also demonstrated that 2.5 nm SiO2 is optimal for the charge tunneling effect and the device has the largest memory window. Moreover, in order to enlarge the memory window of MFIS capacitors, we utilized the stress-enhanced ferroelectric polarization characteristics of Hf0.5Zr0.5O2 to improve the charge-trapping effect. Such a finding demonstrates that the ferroelectric-aided charge-trapping devices are potential to be used in non-volatile memories. [ABSTRACT FROM AUTHOR]

Thermal management has become more critical as semiconductor devices are miniaturized. In metal–oxide–semiconductor field-effect transistors, the problem is the reduction in electron mobility in the channel layer owing to the temperature rise caused by heat generation near the channel-drain region. Focusing on the mean free paths of phonons and electrons in Si, nanostructures of a few 10 nm may only hinder heat propagation without affecting electron transportation. Therefore, inserting nanostructures into the channel layer may prevent a temperature rise and maintain a higher electron mobility. To discuss the relationship between the spacing between the nanopillars (NPs) and the heat generation and carrier behavior of the Si-NP/SiGe composite film, samples with NP spacings of 13, 27, or 47 nm were prepared. We previously confirmed that the thermal conductivity of the Si-NP/SiGe composite film decreased as NP spacing narrowed. The NPs scattered phonon propagation and suppressed heat propagation. However, carrier transport properties such as electrical conductivity, carrier mobility, and carrier lifetime have never been discussed. The laser heterodyne photothermal displacement method was used to examine the effect of nanostructures on carrier mobility and carrier lifetime of Si-NP/SiGe composite films. We observed that the carrier lifetime became longer when the NP spacing was comparable to the electron mean-free path of approximately 27 nm. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistors (CNTFETs) have been considered a strong candidate for post-Si era electronics due to the virtues of higher speed, lower power consumption, and multiple functionalities. The interface analysis based on the top gate structure has made little progress and lacks a reliable charge trap characterization model suitable for carbon tube devices. Quantitative extraction and analysis of the interface state are crucial for the integration of top-gate devices. Herein, a 5 nm thick Y2O3 thin film was selected as the gate dielectric layer in the top-gate CNTFETs device, and a post-annealing process in air ambience was utilized to optimize the Y2O3-CNT interface. A series of device performance evaluation results indicated that the post-annealing process in air ambience can effectively improve the on-state current and reduce the threshold voltage and subthreshold swing of the device, which are derived from diffusion of oxygen atom in the Y2O3 layer and optimization of the interface of Y2O3-CNT. Specifically, the maximum mobility, subthreshold swing, and threshold voltage are calculated to be 29 cm2/V s, 103 mV/dec, and −0.1 V, respectively, and the interface state density is reduced from 2.68 × 1012 to 1.51 × 1012 cm−2 in the gate insulator. These results not only are important to understand the dielectric impact on CNTFET devices but also are useful for future materials' development and device optimization for high-performance CNT-based electronics. [ABSTRACT FROM AUTHOR]

The model of lateral β-Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) was established using Sentaurus Technology Computer Aided Design software. The gate-to-drain distance of the device was 13.7 μm, and the breakdown voltage was 1135 V. The single event effect simulation model caused by heavy ion irradiation was introduced, and the effects of heavy ions' incident position, angle, drain bias voltage, and linear energy transfer on the single event effect were studied. It is found that x = 7.7 μm is the sensitive location of the single event effect at the gate corner near the drain side and the peak value of the transient current is 177 mA/mm. The effect of the terminal structure of the field plate on the transient effect of the single event effect of β-Ga2O3 MOSFET is studied. It is also found that the sensitive position of the single event effect of the conventional structure, gate-field plate structure, and gate–source composite field plate structure is around x = 7.7 μm when VDS = 10 V. The peak transient currents obtained are 177, 161, and 148 mA/mm. The single event effect pulse current of the three structures increases with an increase in the drain bias voltage, while the peak pulse current of the conventional structure is larger than that of the gate-field plate structure and the gate–source composite structure. The research shows that the terminal structure of the field plate is reliable means to reduce the single particle effect. [ABSTRACT FROM AUTHOR]

By employing a mixed SnO2 + Sn source, we demonstrate suboxide molecular beam epitaxy (S-MBE) growth of phase-pure single-crystalline metastable SnO (001) thin films on Y-stabilized ZrO2 (001) substrates at a growth rate of ∼1.0 nm/min without the need for additional oxygen. These films grow epitaxially across a wide substrate temperature range from 150 to 450 °C. Hence, we present an alternative pathway to overcome the limitations of high Sn or SnO2 cell temperatures and narrow growth windows encountered in previous MBE growth of metastable SnO. In situ laser reflectometry and line-of-sight quadrupole mass spectrometry were used to investigate the rate of SnO desorption as a function of substrate temperature. While SnO ad-molecule desorption at TS = 450 °C was growth-rate limiting, the SnO films did not desorb at this temperature after growth in vacuum. The SnO (001) thin films are transparent and unintentionally p-type doped, with hole concentrations and mobilities in the range of 0.9–6.0 × 1018 cm−3 and 2.0–5.5 cm2 V−1 s−1, respectively. These p-type SnO films obtained at low substrate temperatures are promising for back-end-of-line (BEOL) compatible applications and for integration with n-type oxides in pn heterojunctions and field-effect transistors. [ABSTRACT FROM AUTHOR]

The optimization of graphene field-effect transistors (GFETs) for high-frequency applications requires further understanding of the physical mechanisms concerning charge carrier transport at short channel lengths. Here, we study the charge carrier transport in GFETs with gate lengths ranging from 2 μ m down to 0.2 μ m by applying a quasi-ballistic transport model. It is found that the carrier mobility, evaluated via the drain–source resistance model, including the geometrical magnetoresistance effect, is more than halved with decreasing the gate length in the studied range. This decrease in mobility is explained by the impact of ballistic charge carrier transport. The analysis allows for evaluation of the characteristic length, a parameter of the order of the mean-free path, which is found to be in the range of 359–374 nm. The mobility term associated with scattering mechanisms is found to be up to 4456 cm 2 /Vs. Transmission formalism treating the electrons as purely classical particles allows for the estimation of the probability of charge carrier transport without scattering events. It is shown that at the gate length of 2 μ m, approximately 20% of the charge carriers are moving without scattering, while at the gate length of 0.2 μ m, this number increases to above 60%. [ABSTRACT FROM AUTHOR]

Understanding and improving the contact resistance of two-dimensional materials for the fabrication of next-generation devices is of vital importance to be able to fully utilize the new physics available in these materials. In this work, eight different contact metals (Ag, Au, Cr, Cu, In, Mo, Ni, and Ti) have been investigated using the same sample of monolayer MoS2. Through the fabrication and testing of multiple, identically sized field-effect transistor devices per contact metal, we compensate for large variability in electrical properties of as-grown chemical vapor deposition MoS2 and deduce the relative performance of each metal. The general trend of lower work function metals having lower contact resistance holds with In, Ag, and Ti performing the best of the metals tested. Our results are compatible with recent research suggesting that the contact resistance in undoped, monolayer MoS2 is dominated by a lateral junction resistance, and we provide context for how this manifests in device-to-device variation. Multiple orders of magnitude differences in contact resistance are observed between metals and can be explained by this lateral barrier operating in the thermionic-field emission regime. [ABSTRACT FROM AUTHOR]

We report on the numerical and theoretical results of sub-THz and THz detection by a current-driven InGaAs/GaAs plasmonic field-effect transistor (TeraFET). New equations are developed to account for the channel length dependence of the drain voltage and saturation current. Numerical simulation results demonstrate that the effect of drain bias current on the source-to-drain response voltage (dU) varies with the device channel length. In a long-channel TeraFET where plasmonic oscillations cannot reach the drain, dU is always positive and rises rapidly with increasing drain current. For a short device in which plasmonic oscillations reach the drain, the current-induced nonuniform electric field leads to a negative response, agreeing with previous observations. At negative dU, the amplitude of the small-signal voltage at the drain side becomes larger than that at the source side. Thus, the device effectively serves as a THz amplifier in this condition. Under the resonant mode, the negative response can be further amplified near the resonant peaks. A new expression of dU is proposed to account for this resonant effect. Based on those expressions, a current-driven TeraFET spectrometer is proposed. The ease of implementation and simplified calibration procedures make it competitive or superior compared with other TeraFET-based spectrometers. [ABSTRACT FROM AUTHOR]

The application of germanium (Ge)-based transistors has long been restricted by the poor reliability of the gate dielectrics. One solution proposed in the experiment is capping the GeO 2 layer with high-k dielectrics and further doping the dielectric with yttrium (Y) atoms. However, the strategy only works at a very small doping concentration window, and the underlying mechanism remains unclear. Here, we carry out first-principles calculations on a concrete Ge/GeO 2 /ZrO 2 stack to study the structural and electronic properties of various defects before and after Y-doping and further calculate their exact charge-trapping rates by the Marcus charge transfer theory. We show that the Y atoms can effectively weaken the charge-trapping capability of vacancy defects in the ZrO 2 layer, but on the other hand, they can induce some new types of active defects if the density is high. In addition, it is found that the Y atoms can have a very different effect even when doped to the same material. These results indicate that a precise control of the doping position and doping concentration is necessary to promote the reliability of Ge transistors. [ABSTRACT FROM AUTHOR]

The recent discovery of van der Waals (vdW) ferroelectric materials has inspired their incorporation into numerous nonvolatile technologies and shown potential promise for various device applications. Here in this perspective, we evaluate the recent developments in the field of vdW ferroelectric devices, with discussions focusing on vdW heterostructure ferroelectric field-effect transistors and vdW ferroelectric memristor technologies. Additionally, we discuss some of the many open questions that persist in these technologies and possible pathways research can take to answer these questions and further advance the understanding of vdW ferroelectric materials. [ABSTRACT FROM AUTHOR]

The precise control of Mg concentration ([Mg]) in p-type GaN layers from 2.3 × 1016 to 2.0 × 1019 cm−3 was demonstrated by halide vapor phase epitaxy (HVPE) on n-type GaN (0001) freestanding substrates. [Mg] in GaN layers could be controlled well by varying the input partial pressure of MgCl2 formed by a chemical reaction between MgO solid and HCl gas under the thermodynamic equilibrium condition. In the sample with [Mg] of 2.0 × 1019 cm−3, a step-bunched surface was observed because the surface migration of Ga adatoms was enhanced by the surfactant effect of Mg atoms. The samples show high structural qualities determined from x-ray rocking curve measurements. The acceptor concentration was in good agreement with [Mg], indicating that almost all Mg atoms act as acceptors. The compensating donor concentrations in the samples were higher than the concentrations of Si, O, and C impurities. We also obtained the Mg acceptor level at a sufficiently low net acceptor concentration of 245 ± 2 meV. These results show that the HVPE method is promising for fabricating GaN vertical power devices, such as n-channel metal–oxide–semiconductor field-effect transistors. [ABSTRACT FROM AUTHOR]

The gate defect of the ferroelectric HfO2-based Si field-effect transistor (Si FeFET) plays a dominant role in its reliability issue. The first-principles calculations are an effective method for the atomic-scale understanding of gate defects. However, the first-principles study on the defects of FeFET gate stacks, i.e., the metal/orthorhombic-Hf0.5Zr0.5O2/SiOx/Si structure, has not been reported so far. The key challenge is the construction of metal/orthorhombic-Hf0.5Zr0.5O2/SiOx/Si gate stack models. Here, the atomic structure and defect property of orthorhombic-Hf0.5Zr0.5O2/SiO2/Si gate stack are systematically studied by first-principles calculations. We use the Hf0.5Zr0.5O2(130) high-index crystal face as the orthorhombic ferroelectric layer and construct a robust atomic structure of the orthorhombic-Hf0.5Zr0.5O2/SiO2/Si gate stack without any gap states based on the electron counting rule. The calculated band offsets show that this gate structure is of type-I band alignment. Furthermore, the formation energies and charge transition levels (CTLs) of defects reveal that the oxygen vacancy defects are more favorable to form compared with other defects such as oxygen interstitial and Hf/Zr vacancy, and their CTLs are mainly localized near the Si conduction band minimum and valence band maximum, in agreement with the reported experimental results. The oxygen vacancy defects are responsible for charge trapping/de-trapping behavior in Si FeFET. This work provides an insight into gate defects and paves the way to carry out the first-principles study of ferroelectric HfO2-based Si FeFET. [ABSTRACT FROM AUTHOR]

As a one-dimensional structure with atomically thin sidewalls, charge transport in carbon nanotubes can be regarded as a surface phenomenon. As such, perturbations from the surrounding environment can have a dramatic impact on transport and consequently on the device behavior of carbon nanotube field-effect transistors (CNTFETs). Importantly, this includes effects from device fabrication processes like contact metallization. With this as motivation, several aspects of contact metallization are investigated herein. First, it is found that ON current in n-type CNTFETs is enhanced to the level of p-type CNTFETs through the utilization of titanium as an adhesion layer, a result of improved wetting. Effects of different metallization techniques, namely, thermal and electron-beam evaporation, are also explored in p-type devices using titanium/palladium/gold contacts. It is found that thermal metallization consistently produces devices with higher ON current. In-depth analysis of the transfer characteristics reveals that this is due to radiation effects encountered during electron-beam processing, resulting in channel scattering and a decreased transconductance in the devices. This effect is particularly severe upon gold processing, and attempts to heal this device degradation through annealing proved unsuccessful. All studies presented here are conducted through the analysis of a large number of nanotube devices, giving a degree of confidence to the average results. Additionally, only device parameters that can be directly extracted from the transfer characteristics are analyzed. Assumptions including nanotube diameter, capacitance, and nanotube number per device are not made. Results from this study provide recommendations for optimizing CNTFET performance as it relates to contact metallization. [ABSTRACT FROM AUTHOR]

Thanks to their formidable electron transport properties, III–V compound semiconductors have established themselves as a possible alternative to strained-Si as future n-type logic switches. To predict the performance of such transistors, device simulators that can capture the peculiarities of the III–V band structure at low computational cost are required. In particular, their strong band non-parabolicity (NP) calls for advanced models going beyond the standard effective mass approximation (EMA). Previous studies have suggested ways to include NP effects into quantum transport calculations in the ballistic limit. Here, such a model is extended to account for electron–phonon interactions. It combines the non-equilibrium Green's function formalism and the EMA with NP corrections. The proposed method is validated through simulations of InGaAs nanowire field-effect transistors. The results are compared to full-band tight-binding calculations and to the solution of the subband Boltzmann transport equation, showing excellent agreement. [ABSTRACT FROM AUTHOR]

Progress in the development of nanometer scaled Fin Field Effect Transistor (FinFET) devices is affected by a lack of understanding of relevant dopant diffusion phenomena due to limited experimental data. In particular, 2D dopant potential mapping by electron holography in 3D FinFET devices has been challenged by the overlap of electrically active fins, metal films, and dielectric films in the electron beam direction. This paper presents methodology on how to map dopant potential in modern FinFET devices. A custom-device structure was developed, which preserved all essential features of the device manufacturing process. The dopant reconstruction method is suggested to account for the presence of materials other than silicon fin between fins. A comparison of lateral dopant potential profiles with device simulations offers agreement within 0.32 V. Compositional non-uniformity of materials between fin devices is identified as the main limiting factor. A further reduction of compositional non-uniformity should allow for quantitative 2D dopant potential mapping with high sensitivity to probe the effects of dopant segregation, deactivation, and diffusion kinetics in 3D FinFET devices at the nanometer scale. [ABSTRACT FROM AUTHOR]

This research article proposes a deep learning framework that addresses two major hurdles in adopting deep learning techniques for solving physics-based problems. One is the requirement of a large data set for training the deep learning (DL) model and another is the consistency of a DL model with the physics of a phenomenon. The framework is generic that can be applied to model a phenomenon in physics if its behavior is known. A semi-supervised physics guided neural network (SPGNN) has been developed based on our framework to demonstrate the concept. SPGNN models the I–V characteristics of gallium nitride based high electron mobility transistors (GaN HEMTs). A two-stage method has been proposed to train a DL model. In the first stage, the DL model is trained via an unsupervised learning method using the analytical physics-based model of a field-effect transistor (FET) as a loss function of the DL model that incorporates the physics of the FET in the DL model. Later, the DL model is fine-tuned with a small set of experimental data in the second stage. Performance of SPGNN has been assessed on various sizes of the data set with 100, 500, 1000, 1500, and 2000 samples. SPGNN significantly reduces the training data requirement by more than 80% and provides better performance than a traditionally trained neural network (TTNN), even for the unseen test data set. SPGNN predicts 32.4% of the unseen test data with less than 1% of error and only 0.4% of the unseen test data with more than 10% of error. [ABSTRACT FROM AUTHOR]

Raman spectroscopy is an effective tool for stress and compositional metrology in the semiconductor industry. However, its application toward decoupling a complex stress state in semiconductor materials requires the use of liquid immersion lenses that are process line incompatible. In this work, a practical design concept for off-axis Raman spectroscopy is presented. By tilting the incident light away from the normal incident axis, forbidden Raman modes can be accessed allowing determination of the in-plane stress tensor in semiconductor materials. Furthermore, we benchmark off-axis Raman spectroscopy against oil-immersion Raman spectroscopy for stress characterization in 20 nm-wide strained Ge fin field-effect transistor channels. We demonstrate that off-axis Raman allows anisotropic stress metrology without reliance on liquid immersion lenses, highlighting its viability in the process line. The stress state is validated through nanobeam diffraction measurements. [ABSTRACT FROM AUTHOR]

We present a computational study on the electrical behavior of the field-effect transistor based on vertical graphene-hBN- χ 3 borophene heterostructure and vertical graphene nanoribbon-hBN- χ 3 borophene nanoribbon heterostructure. We use nonequilibrium the Green function formalism along with an atomistic tight-binding (TB) model. The TB parameters are calculated by fitting tight-binding band structure and first-principle results. Also, electrical characteristics of the device, such as ION/IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. We show that the increase of the hBN layer number decreases subthreshold swing and degrades the intrinsic gate-delay time. The device allows current modulation 177 at room temperature for a 1.2 V gate-source bias voltage. [ABSTRACT FROM AUTHOR]

In this paper, dry etched vertical nanowires (VNWs) are used in transmission line/transfer length analysis to study the contacts of gate-all-around devices for future technology nodes. VNW resistors with Mo and Pd based metal stack contacts to p-InGaAs show Schottky behavior, unlike the planar counterpart. The resistance for Mo contact is higher than Pd, however, Pd was found to form an alloy with InGaAs at temperatures as low as 190 °C, and the length of Pd diffusion into the InGaAs increased at smaller NW dimensions, hindering future scalability. The minimum extracted specific contact resistivity (ρC) values are 1.6 × 10−5 Ω cm2 (Mo) and 4.2 × 10−6 Ω cm2 (Pd) for a doping level of 1 × 1019 cm−3. An apparent dependence of ρC on the NW diameter was also observed. This has been attributed to the surface states under the un-gated region of NW devices and found to dominate at smaller diameters. An analytical model to account for such geometrical effects has also been developed and validated with technology computer-aided design simulations. The analysis presented in this paper effectively captures the 3D aspects of an NW contact at nanoscale dimensions and can be applied irrespective of the semiconductor and contact metal used. [ABSTRACT FROM AUTHOR]

The potential barrier height at the interface formed by a metal contact and multiple one-dimensional (1D) quasi-ballistic channels in field-effect transistors is evaluated across different carbon nanotube and nanowire device technologies by means of a Landauer–Büttiker-based extraction methodology (LBM) adapted for multiple 1D-channels. The extraction methodology yields values for an effective Schottky barrier height and a gate coupling coefficient, an indicator of the device working at the quantum capacitance limit. The novel LBM-based approach embracing the mechanisms in 1D electronics is compared to the conventional activation energy method not considering such effects. The latter approach underestimates the potential barrier height at metal–channel interfaces in comparison to the novel methodology. A test structure based on a displaced gate device is proposed based on numerical device simulation results toward an improved accuracy of the method. [ABSTRACT FROM AUTHOR]

Normally Off diamond field-effect transistor (FET) is demanded for energy saving and safety for practical application. Metal/diamond Schottky junction serving as the gate is a simple and effective approach to deplete holes under the gate, whereas low Schottky barrier height (SBH) is undesirable. In this work, a dual-barrier Schottky gate hydrogen,oxygen-terminated diamond (H,O-diamond) FET (DBG-FET) with Al gate was realized. Normally Off DBG-FET with enhanced SBH and reduced leakage was achieved. H,O-diamond, which was defined by x-ray photoelectron spectroscopy (XPS) technique, was realized by ultraviolet ozone (UV/O3) treatment with nanoparticle-Al mask. The enlarged SBH of 0.94 eV owing to the C–O bond minimized the diode reverse current and nicely shut down the DBG-FET at zero gate bias. Moreover, the forward current of diode can be well-reduced by hundred times ascribed to oxidized Al nanoparticles during the UV/O3 process. Based on this diode gate structure, the maximum drain current density, transconductance, on/off ratio, and subthreshold swing of the normally off DBG-FET are 21.8 mA/mm, 9.1 mS/mm, 109, and 96 mV/dec, respectively. The DBG-FET is expected to promote the development of normally off diamond FETs. [ABSTRACT FROM AUTHOR]

High dose irradiation effects of gamma-rays up to 17 MGy (H2O) on 4H-SiC junction field effect transistors (JFETs) were investigated. Due to the irradiation, gradual positive threshold voltage (Vth) shift as high as 0.5 V and continuous decrease in transconductance gm were observed. In addition, Vth instability and hysteresis appeared for the irradiated JFETs when the gate voltage (VG) sweep direction, sweep interval, i.e., averaged sweeping rate, sweep range, and delay time were changed. Increase of VG interval attributed to positive Vth shift for both forward and reverse directions, whereas narrowing of sweep range and increase of delay time resulting in a more noticeable negative shift of Vth for the reverse direction. Such Vth hysteresis indicates that capture and release of carriers predominantly took place via hole traps formed around the gate region due to high dose gamma-ray irradiation. [ABSTRACT FROM AUTHOR]

The interest in germanium (Ge) is rising for use in field-effect transistors, (space) photovoltaics, and silicon photonics. Suppressing and understanding carrier recombination at the Ge surface are vital for the performance of Ge in these applications. In this work, we have investigated the surface recombination at various germanium–dielectric interfaces (Ge/Al2O3, Ge/SiNx, Ge/GeOx/Al2O3, and Ge/a-Si:H/Al2O3). For this purpose, we performed corona-lifetime experiments and extracted a set of recombination parameters by fitting the data with the theoretical Girisch model. To keep the model straightforward, the distributions of the capture cross sections and the interface defect density (D i t) were parameterized. The importance of each parameter in these distributions was examined so that a minimum number of parameters was distilled: the so-called fundamental recombination velocities (S p 0 and S n 0 ) and the magnitude of the D i t near the valence and conduction band edge (D it , VB and D it , CB ). These parameters form together with the fixed charge density (Q f) , the spatial distribution thereof (σ Q) , and a minimum surface recombination velocity (S min ) , a set of parameters that can well describe our experimental data. Relevant insights were obtained from the experiments, with highlights including a Ge/GeOx/Al2O3 stack with virtually no fixed charge density, a highly passivating Ge/a-Si:H/Al2O3 stack, and a negatively charged Ge/SiNx stack. The findings in this study are valuable for applications where a more profound understanding of recombination at Ge surfaces is of concern, such as in photonics, photovoltaics, and nano-electronics. [ABSTRACT FROM AUTHOR]