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This paper presents a theoretical analysis of the second‐breakdown phenomenon. The analysis makes the use of the coupled current‐continuity, the Fourier heat‐flow, and the Poisson equations. The geometry used in the analysis allows the directions of current and heat flow to be separated self‐consistently. The trigger temperature is derived and a plot of its variation with respect to applied voltage is given. The approximate expressions for the steady‐state voltage states is also given.

The current‐voltage characteristics of the p+np+ diode are derived for bias voltages below reach‐through condition. The electron current continuity equation is used to find the relationship between the voltage across the forward‐biased junction and the total applied voltage. For a narrow central neutral region a joint probability is defined so as to give the probability that a carrier has a velocity above some minimum value and travels across the neutral region without being scattered. The thermionic emission current is then obtained, the J‐V characteristics is plotted, and the singularity from the conventional theory at the reach‐through is then removed.

A very thick gate oxide layer 1.1 μm is intentionally used to enhance the fringing field effect around the edge of oxide layer. Then, the slopes of the Id‐VG curves in the linear region are obtained for various substrate reverse‐biased voltages VBG. The slopes are an increasing function of ‖VBG‖, which indicates that the effective capacitance per unit area of the oxide layer also increases with ‖VBG‖.

By considering the finite distance of the semiconductor space‐charge center away from the Si‐SiO2 interface, a modified expression of the flat‐band voltage (VFB) due to the surface charge density (Qss) is derived. For the accumulation and strong inversion cases, the conventional expression Qss/Co, is valid, however, under the depletion condition the modified expression will be used. The VFB is found to be nonlinearly related to Qss, and the expression may be deduced to the conventional form only in the limit that the Qss is low, the semiconductor is heavily doped, and the oxide thickness is large.

An external controllable dc negative‐differential‐resistance (NDR) device is presented. The device structure is composed of a conventional MOST and two parasitic transistors, which are internally coupled together. The mechanism of NDR is found to be initiated by both the breakdown phenomena at the drain junction and the negative‐feedback circuit from the drain to the gate electrode through an externally connected resistor. Both the experimental observations and qualitative physical interpretations are given.