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Neural networks in brain are structured in a 3-D space, and the networks are evolved through development and learning, whereas 2-D crossbars have essentially been optimized for fully-connected neural network, which results in significant increase of unused memristors. Here we present a prototype of molecular neural networks on wetware consisting of a space-free synaptic medium immersed in monomer solution. In the medium, conductive polymer wires are grown between multiple electrodes through learning only when necessary; i.e., no polymer wire is pre-placed unlike present 2-D crossbar devices. Through experiments we found necessary growth conditions for synaptic polymer wires. We first demonstrated learning of simple Boolean functions and then data-encoding tasks by using our system consisting of the synaptic media and their external controllers. These results are valuable to expand a concept of space-free synapse development; i.e., extending our 2-D synaptic media to 3-D is possible in principle.

The trends in AI chip development since 2013 can be divided into two categories of applications: server and edge. As for the server, recently, ASIC chips designed for learning functionalities have become mainstream, with competitively computational performance. However, the limitations of Moore's Law have started to impose themselves on this emerging type of AI chips, creating the need for new technological innovation. Meanwhile, regarding edge AI chips, research on data compression technology is advancing to lower power consumption while maintaining high performance. Further improvements have been made since 2017 in recognition accuracy in binary/ternary; moreover, there has been research on in-memory processing to configure 1 bit by combining memory and arithmetic element, where non-volatile memory can achieve higher performance and lower power consumption. With these backdrops, this paper summarizes the progress made to date in the field of AI chip technology while also identifying the future direction of next-generation technologies.

A neuron MOS (νMOS) vision chip was designed and fabricated for developing high-speed parallel image-processing systems based on cellular-automaton processing. The chip consists of cellular νMOS circuits that implement two fundamental functions in digital image processing: i) cleaning up noise in binary images and ii) detecting edges in the images, in addition to photosensing and image quantizing. Experimental results reveal that the fabricated chip successfully extracted edges from noisy inputs, which demonstrates the great potential of the νMOS vision chip in future image-processing applications.

In this paper, fabrication of a simple analog network for one-dimensional motion detection using the complementary metal-oxide-silicon (CMOS) process is described. The network is constructed with a number of local motion sensors based on biological elementary motion detectors. Experimental and simulation results indicate that the fabricated network computes the local velocity and direction of the moving object in the velocity range of 10-4 m/s to 3.2 ×102 m/s. The results also show that the velocity sensitivity of the network can be changed flexibly. The circuit structure of the network is compact and suitable for highly dense motion sensor arrays.

We propose simple analog MOS circuits producing one-dimensional optical flows aiming at the realization of compact motion-sensing circuits. In the proposed circuit, the optical flow is computed by a number of local motion sensors which are based on biological motion detectors. Mimicking the structure of biological motion detectors made the circuit structure quite simple, compared with conventional velocity sensing circuits. Extensive simulation results by a simulation program of integrated circuit emphasis (SPICE) indicated that the proposed circuits could compute local velocities of a moving light spot and showed direction selectivity for the moving spot, which implies that a high-resolution motion-sensing chip can be realized using standard analog very large-scale integration (VLSI) technology.