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A new processing scheme for the fabrication of sub-100-nm-gate-length vertical nanowire transistors has been developed. InAs transistors with an 11 ×11 nanowire matrix and 80 nm gate length have been realized by this process. The gate length is directly controlled via the thickness of the evaporated gate metal and is thus easily scalable. The demonstrated devices operate in depletion mode, and they show a maximum drive current of about 1 mA and a maximum transconductance of 0.52 mS at Vg=-0.5 V and Vd=1 V.

P-type Schottky barrier Ge nanowire transistors modulated with dopant segregated regions are proposed and studied. The impact of dopant segregated regions on device performance is simulated and investigated with numerical tools. It is revealed that dopant segregation is beneficial to increasing drive current and better utilizing nanowire channel. The OFF-state current is effectively suppressed with high dopant concentration, and the phenomena in the minimum current curves are carefully reinterpreted with carrier transport mechanisms. It is also shown that the dopant segregated regions with moderate length and high concentration can achieve high ON/OFF ratio and low subthreshold slope. Furthermore, we find that the subthreshold slope of long segregation length is insensitive to source/drain barrier heights, and that moderate segregation length helps to obtain lower subthreshold slope as channel length is scaled down.

The drain current vs gate voltage (I D–V G) and drain current vs drain voltage (I D–V D) characteristics of ferroelectric gate-all-around Si nanowire transistors are derived using the drift/diffusion transport theory. It is pointed out that the nonsaturated polarization in the ferroelectric film, which occurs near the drain region in the channel owing to the influence of the applied drain voltage, plays an important role in the calculation of the drain current as well as the polarization near the source region, and a graphical method using analytical expressions for the minor polarization hysteresis loops is presented to calculate the mobile charge density in the nanowire. By numerical analysis, the gate voltage range suitable for memory operation is determined in Si nanowire transistors with ferroelectric poly(vinylidene fluoride–trifluoroethylene) [P(VDF–TrFE)] gate films.

Gate-induced drain leakage (GIDL) in Si nanowire transistors fabricated on silicon-on-insulator substrates is systematically studied. In narrow nanowire transistors, GIDL current is obtained by relatively small potential difference between the gate and the drain due to the superior electrostatic control by gate voltage. On the other hand, variation of GIDL current with gate voltage is drastically reduced in nanowire transistors with the wire width of around 10 nm, which realizes devices with extremely small off-current. The reduction of local electric field around the drain junction due to low impurity concentration in source/drain extensions and the relatively large source/drain parasitic resistance are identified as the main mechanisms of small GIDL current.