Search

Suppressing leak current and blocking Cu diffusion into active Si from Cu through-silicon vias (TSVs) are important requirements for enhancing three-dimensional (3D) LSI performance and reliability. We have proposed and confirmed a cost effective means of enhancing the barrier property of sputtered Ti in high-aspect-ratio Cu-TSVs by simple vacuum annealing at 400 °C for 20 min. The self-formed amorphous TiSi2 at the interface between dielectric SiO2 (along the TSV side-wall) and barrier Ti layer is found to play a positive role in improving the leak current characteristics. As-formed TiSix was partially converted into TiO2 and SiO2 during the vacuum annealing above 200 °C, and nearly vanished after annealing at 400 °C. The immense importance of 400 °C vacuum-annealing is not only in terms of the improvement in the barrier characteristics of the Ti layer, but also it is being a prerequisite for preventing Cu popup in 3D-LSI. Both the X-ray photoelectron spectroscopy (XPS) and current–voltage (I–V) data clearly reveal that this simple vacuum annealing of Cu-TSVs at 400 °C has tremendous potential for implementation in cost-effective via-last 3D integration. [ABSTRACT FROM AUTHOR]

Minimization of the parasitic capacitance arising from Cu–through-Si-vias (TSVs) has been rigorously considered in order to enhance the performances of three-dimensional (3D) LSIs. We have systematically investigated the role of chemical vapor deposited (CVD) polyimide (PI) liner in Cu-TSVs in reducing the TSV capacitance. It is confirmed that CVD grown PI greatly helps to reduce the TSV capacitance as compared to the conventional PECVD-SiO2 liner. In addition to that the presence of very small hysteresis and a negligible flat-band voltage shift along the voltage axis confirms the suitability of PI liner as dielectric in the Cu-TSVs, if it were operated below the bias voltages of ±20 V. In over all, the large reduction in capacitance along with the conformal deposition of PI in the TSVs having less than 3 µm-width with aspect ratios greater than 10 reveals that CVD grown PI has the potential application in the future 3D-LSIs with highly scaled TSV. [ABSTRACT FROM AUTHOR]