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We have developed organic photoconductive film (OPF) CMOS image sensors with pixel structures different from those of a conventional silicon image sensors, in which, the organic thin film for photoelectric conversion and the charge storage part for signal charge accumulation are completely independent. In this paper, we focus on two unique features of the OPF image sensor: (1) technology that realizes over 120 dB simultaneous-capture wide dynamic range, (2) global shutter technology achieving high saturation signals per unit square that is 10 dB higher than that of silicon image sensors with the global shutter function, without sacrificing pixel area. In addition, we have developed a test chip that realizes a high resolution of 8K4K, a high frame rate of 60 fps, a high saturation signals of 450 ke−, and the global shutter function simultaneously. These features of the OPF image sensor will contribute to significant progress in imaging and sensing fields. [ABSTRACT FROM AUTHOR]

We demonstrate a 16-level cell using a nonvolatile oxide semiconductor random access memory test chip based on c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide (CAAC-IGZO) FETs. The memory cell consists of a CAAC-IGZO FET, a p-channel metal–oxide–semiconductor Si FET, and a cell capacitor. Data are written using a threshold voltage cancel write method, and a read circuit composed of voltage followers outputs a read voltage. Using a 200 ns write time of the test chip, the obtained maximum read voltage distribution width is 37 mV in the case of 32768 memory cells. The distributions of 16 read voltages are separated from each other without overlapping, with a single voltage follower exhibiting a maximum read voltage distribution width of 25.3 mV. In the −40 to 85 °C temperature range, the voltage distribution range is 0.13 V, and the variation due to varying temperatures is 0.24 mV/°C. [ABSTRACT FROM AUTHOR]

To achieve both low power consumption and high-speed operation, we fabricated c-axis-aligned crystalline indium–gallium–zinc oxide (CAAC-IGZO) field-effect transistors (FETs) with In-rich IGZO and common IGZO ( in atomic ratio) active layers through a simple process using trench gates, and evaluated their characteristics. The results confirm that 60-nm-node IGZO FETs fabricated through a 450 °C process show an extremely low off-state current below the detection limit (at most 2 × 10−16 A) even at a measurement temperature of 150 °C. The results also reveal that the FETs with the In-rich IGZO active layer show a higher on-state current than those with the common IGZO active layer and have excellent frequency characteristics with a cutoff frequency and a maximum oscillation frequency of up to 20 and 6 GHz, respectively. Thus, we demonstrated that CAAC-IGZO FETs with trench gates are promising for achieving both low power consumption and high-speed operation. [ABSTRACT FROM AUTHOR]

We study the effect of indium–gallium–zinc oxide (IGZO) crystallinity on oxygen vacancies that play an important role in the characteristics of IGZO-based devices. Optical and electrical measurements revealed that deep defect levels due to oxygen vacancies are largely eliminated in c-axis-aligned crystal IGZO (CAAC-IGZO), which has increased crystallinity without clear grain boundaries. In this study, the correlation between crystallinity and oxygen vacancy formation has been examined by first-principles calculations to investigate the effect of oxygen vacancies in IGZO. Furthermore, the likelihood of oxygen vacancy formation at an edge portion of single-crystal IGZO has been verified by observations of oxygen atoms at the edge region of the IGZO film by annular bright-field scanning transmission electron microscopy (ABF-STEM). Experimental and calculation results show that the high crystallinity of IGZO is important for the inhibition of oxygen vacancies. [ABSTRACT FROM AUTHOR]

A dynamically reconfigurable nonvolatile field-programmable gate array (FPGA) with a multi-context (MC) cell array structure that uses three-terminal magnetic tunnel junction (MTJ) devices is proposed. The use of single-ended circuitry together with a 2-transistor and 1-MTJ (2T–1MTJ) context cell allows for the minimization of the area overhead of the context array with nonvolatile storage capability. As the 2T–1MTJ cell has no power line, the leakage current overhead is also minimized. With the proposed implementation, the transistor counts and leakage power during power-on are reduced by 59 and 71%, respectively, compared to the static random-access memory (SRAM)-based implementation using 40-nm CMOS technology. [ABSTRACT FROM AUTHOR]

We report a detailed analysis of the nanoscopic structure of an In–Ga–Zn-oxide (IGZO) thin film deposited at room temperature. Using nanobeam electron diffraction (NBED) with a 1-nm-diameter probe, we analyzed a nanoscopic region of the IGZO thin film in which the diffraction spots of crystal were unobservable in a macroscopic region using selected-area electron diffraction (SAED) with about 300-nm-diameter probe. However, they were clearly recognized in a NBED pattern. They indicate a minute crystalline structure in the film. We further confirm the presence of crystals by observing a NBED pattern with spots distributed with six-fold symmetry in a specimen thickness thinned down to10 nm. To check the effect of the electron-beam irradiation during a transmission electron microscopy (TEM) and NBED measurements, we examine changes in crystal size as a function of the cumulative electron dose. No crystal growth during the electron beam irradiation was observed in the film. These results allow us to conclude that the IGZO thin film is not amorphous but a nanocrystalline (nc)-IGZO thin film, composed of nanometer-size crystals. [ABSTRACT FROM AUTHOR]

A multi-context (MC) field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0 µm c-axis aligned crystalline In–Ga–Zn–O (CAAC-IGZO) field-effect transistor (FET), which is one of CAAC oxide-semiconductor (OS) FETs, and a 0.5 µm complementary metal oxide semiconductor (CMOS) FET. The FPGA achieves a 20% layout area reduction in a routing switch and an 82.8% reduction in power required to retain data of configuration memory (CM) cells at 2.5 V driving compared to a static random access memory (SRAM)-based FPGA. A controller for fine-grained PG can be implemented at an area overhead of 7.5% per programmable logic element (PLE) compared to a PLE without PG. For each PLE, the power overhead with fine-grained PG amounts to 2.25 and 2.26 nJ for power-on and power-off, respectively, and break-even time (BET) is 19.4 µs at 2.5 V and 10 MHz driving. [ABSTRACT FROM AUTHOR]

We report, in this paper, that crystalline In–Ga–Zn-oxide (IGZO) can be formed over an amorphous surface or over an uneven surface by a sputtering process at lower than 500 °C through the purification of IGZO. Crystalline IGZO, in which no clear grain boundary is observed, shows c-axis alignment but random a- and b-axis orientations without alignment. This crystal morphology differs from other morphologies that have been known thus far, such as single crystal and polycrystal morphologies. Our model for understanding the formation of this crystal morphology [c-axis-aligned crystal (CAAC)] is also discussed. Upon thermal annealing of a deposited film at lower than 500 °C, nanocrystal regions remaining in the CAAC can be converted into the CAAC structure. Accordingly, Ioff can be at the yA/µm (10−24 A/µm) level at 85 °C. It has been proven that by utilizing normally-off characteristics even with L/W = 40 nm/40 nm (actual size: L/W = 68 nm/34 nm), the fabrication of a three-dimensional (3D) LSI with a 3D oxide semiconductor/Si hybrid structure is feasible. [ABSTRACT FROM AUTHOR]