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Twelve-channel vertical-cavity surface-emitting laser (12-ch VCSEL) chips are heterogeneously self-assembled on Si and glass wafers using water surface tension as a driving force. The VCSEL chips have a high length-to-width aspect ratio, that is, 3 mm long and 0.35 mm wide. The VCSEL chips are precisely self-assembled with alignment accuracies within 2 ?m even when they are manually placed on liquid droplets provided on the host substrate. After the self-assembly of the VCSEL chips and the subsequent thermal compression, the chips successfully emit 850 nm light and exhibit no degradation of their current?voltage (I?V) characteristics.

A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal–oxide–semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal–oxide–semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.

To establish liquid-assisted assembly processes applicable to heterogeneous system integrations, we present flip-chip self-assembly of dies with Cu/Sn microbumps using the difference in droplet wetting between hydrophilic and hydrophobic areas. Flip-chip self-assembly is assisted by a water-soluble flux that has high surface tension comparable to that of pure water and contains an additive of a reducing agent for metal oxides. Control of the additive concentration in the flux provides high wettability contrast that enable spontaneous and precise alignment of chips to hydrophilic areas formed on substrates within 5 µm in alignment accuracy. In the subsequent chip bonding process, the reductant can eliminate the metal oxide layer and improve the solder wettability of Sn to the corresponding electrode pads formed on the chips. In addition, we confirm, through electrical characteristic evaluation after thermal compression bonding, that the resulting daisy chain formed between the substrates and self-assembled chips with the flux shows sufficiently low contact resistance of below 20 mΩ/bump without disconnection.

A new nonvolatile memory with high density and high work-function metal nanodots, metal nanodot (MND) memory, was proposed and fundamental characteristics of MND capacitor were evaluated. In this work, a nanodot layer of FePt with high density and high work-function (~5.2 eV) was fabricated as a charge storage site in nonvolatile memory, and its electrical characteristics were evaluated for the possibility of nonvolatile memory in view of cell operation by Fowler–Nordheim (FN) tunneling. Here, a nanodot FePt layer was controlled as a uniform single layer with dot size of under ~2 nm and dot density of ~1.2×1013/cm2. Electrical measurements of metal–oxide–semiconductor (MOS) structure with FePt nanodot layer shows a threshold voltage window of ~6 V using FN programming and erasing, which is satisfactory for operation of the nonvolatile memory. Furthermore, this structure provides better data retention characteristics compared to other metal dot materials with similar dot density in our experiments. From these results, it is expected that this nonvolatile memory using an FePt nanodot layer with high dot density and high work-function can be a candidate structure for the future nonvolatile memory.

A novel optical interposer with optical interconnections is proposed for integrating three-dimensional (3D) LSI chips on this interposer. Vertical-cavity surface-emitting laser diode (VCSEL) chips and photo diode (PD) chips are buried in the optical interposer with polymeric optical waveguides. The VCSEL is 0.25 mm in width, 0.35 mm in length, and 0.15 mm in height. We realize precise passive alignment between the optical waveguides and the VCSEL/PD chips using two-step alignment processes consisting of cavity-assisted positioning and the subsequent surface-tension-powered self-assembly with a molten solder. In addition, we demonstrate the basic operation of the buried VCSEL chips in the optical interposer through tapered through-silicon vias (TSVs). The tapered TSVs are successfully formed by copper electroplating and are 64 µm in top width, 34 µm in bottom width, and 168 µm in length.

In this paper, we describe a fundamental study of a complementary metal oxide semiconductor (CMOS) image sensor for a three-dimensional (3D) image-processing system. We proposed a pixel circuit with correlated double sampling (CDS) and high-speed image capturing for high-speed image processing. The CDS and high-speed image-capture circuit should be realized simultaneously to allow high-speed image processing. The pixel circuit can realize CDS and high-speed image-capture functions simultaneously. The CDS and high-speed image capturing are realized by using a pixel sample hold capacitor and shared coupling capacitor. Appending extra capacitors causes the pixel circuit size to become large in the two-dimensional (2D) CMOS image sensor. We proposed a 3D CMOS image sensor that can reduce the pixel circuit size and the electrical wiring length and increase the fill factor, even with CDS and high-speed image capturing. Therefore, small, high-speed parallel-processing systems can be realized by using our 3D CMOS image sensor. We fabricated the prototype 2D pixel circuit with CDS and high-speed image capturing. The prototype pixel circuit is successfully implemented in the simultaneous function. We believe the proposed pixel circuit is very effective for 3D CMOS image processing.

We propose a novel Cu spiral inductor with an FePt magnetic nanodot (MND) layer of FePt magnetic nanodots dispersed in SiO2 film by self-assembled nanodot desposition (SAND). We expected an increase in inductance by adopting an MND layer. Nanodot sizes ranging from 2.5 to 3.5 nm in diameter can be well controlled. By optimizing thermal annealing conditions, we formed an FePt MND film with an electromagnetic permeability of 7.7 for passive devices used in a standard radio-frequency integrated circuit (RFIC) process. The quality factors of various spiral inductors were simulated and compared with the measured quality factors of the Cu spiral inductors we fabricated. In addition, the high-frequency characteristics of Cu spiral inductors were successfully observed.

In order to realize low cost and high density packaging technology, we propose a new wafer scale chip-on-chip (W-COC) packaging technology using the adhesive injection method. In W-COC packaging technology, chip-on-chip modules more than two hundreds are simultaneously formed at the wafer level. In addition, we can significantly improve the chip performance, because small micro-bumps, more than one million, can be formed on a chip and consequently a number of vertical interconnections can be formed between the two bonded chips. Therefore, it is very easy to introduce the parallel processing function in a W-COC module. Using this technology, we propose a new multichip module (MCM) consisting of single or multiple memory chips directly attached to a logic chip. In this paper, we describe key technologies to realize this new multichip module. We fabricated the W-COC test module and investigated its electrical performance using a micro-bump chain.

The pretilt angle (Θ p) of nematic liquid crystals (LCs) could be controlled with alignment layer (AL) polyimides (PIs) and/or LCD processes in the case that a cell gap and a rubbing condition are fixed. Θ p was increased by introducing long, linear alkyl side chains and/or other nonpolar groups to the AL polyimide. On the other hand, Θ p was decreased by modifying the polyimide surfaces (with UV exposure or O2 plasma) and LCD processes such as heating or cleaning the rubbed polyimide and annealing the LC-filled cell. Thus, the AL polyimide and the LCD process can be designed so as to obtain a desired pretilt angle, which is important in applications. In the UV-type two-domain twisted nematic approach for wide-viewing angle LCDs, two different Θ ps were obtained in one pixel and a mechanism for modifying the Θ p was discovered. Upon UV-exposing the PI films, aromatic or conjugated radicals with long lifetimes (greater than 2 weeks) were generated and some side chains were removed, and these PI surfaces subsequently became more polar since polar functional groups such as OH were introduced. The Θ p of ZLI-5080 on the UV-exposed/rubbed PI film decreased by 4.5°–8.8° in comparison with that on the rubbed film probably because the lower steric repulsion and greater electronic attraction would decrease the Θ p.