18 results on '"Shuo-Wei Chen"'
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2. A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology.
3. A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur.
4. 26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency.
5. 29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur.
6. 16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS.
7. 10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation.
8. A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency.
9. Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee.
10. A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling.
11. A fractional-N digital PLL with background-dither-noise-cancellation loop achieving
12. A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving
13. A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS.
14. 10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving
15. 27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS.
16. A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC.
17. A calibration-free 800MHz fractional-N digital PLL with embedded TDC.
18. A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN.
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