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This paper describes the debug and analysis process of a challenging case study from wafer foundry which involved a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide with no detection signal from inline monitoring vehicles. It highlights the need for failure analyst to always be inquisitive and to deep dive into the failure symptoms to value-add the fab in discovering the root cause of the failure in challenging situation where information is limited.

As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.

This paper presents a case study on photon emission from metals and demonstrates the capability of Emission Microscopy Si-CCD camera to detect micro metal bridges on functional failures of Analog devices.

It is difficult to simulate functional failures using static analysis tools, therefore, debugging and troubleshooting devices with functional failures present a special challenge for failure analysis (FA) work and often result in a root-cause success rate is quite low. In this paper, the application of advanced FIB circuit edit (CE) processes combined the static FA analysis yielded successful localization of a bipolar junction transistor (BJT) device soft failure. Additional FA techniques were incorporated within the FA flow, resulting in characterization of the electrical behavior of a suspected transistor and detection of an abnormal implant profile within the active area.

Dynamic Laser Stimulation (DLS) fault isolation techniques involve using an Automated Test Equipment (ATE) to run the device under certain test patterns together and a scanning laser beam to localize sites sensitive to laser stimulation. Such techniques are proven effective for localizing soft failures. In this paper, we demonstrate the feasibility of using such dynamic techniques for functional hard failures and design debug applications. We illustrate experimentally the significance of achieving sufficient signal to noise ratio (SNR) before such applications can be realized effectively, due to the large irregular noise that couples through as the functional pattern is run. We adopted a combination of hardware noise reduction and test program modification to overcome this challenge.

A system-on-chip processor (90 nm technology node) was experiencing a high basic function failure rate. Using a lab-based production tester, laser assisted device alteration, nanoprobing, and physical inspection; the cause of failure was traced to a single faulty P channel transistor. The transistor had been partially subjected to N doping due to poor photo-resist coverage caused by halation.

Specialized structures have been developed to understand how interconnect and via would link together in a circuit to bring out the weakest link in the interconnect-via system. This article reports a phenomenon where electromigration occurred in an actual circuit with signal lines connected by individual vias. A prediction is made into the weak link in the via-Interconnect system based on real time product. In the interconnect-via system used, the TiW barrier blocked the material flow from M2 to Ml. W plugs would block the material flow as they do with the barrier layers and the failures would occur at the via to interconnect interface as noticed in this case. Depending on the electron flow through the via, the material will either accumulate at the via-interconnect interface, which will induce inter-metal dielectric cracks, or deplete, causing discontinuity (opens) of the interconnect lines.

In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the < 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the < 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.