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This article presents a microstrip implementation of a manifold multiplexer. The design procedure is based on evaluation, through an efficient synthesis algorithm recently proposed, of the characteristic polynomials of the triplexer, including the channel filters. Both the manifold and channel filters parameters are also available at the end of the synthesis. This approach, based on polynomial modeling of the triplexer, has been experimentally vali-dated for the first time through a practical implementation in planar technology. The fabri-cated prototype consists of three channel filters of third order centered at 1.84, 1.95, and 2.14 GHz, with bandwidth of 75, 60, and 60 MHz respectively. This work illustrates in detail the design and implementation of the practical triplexer, starting from the initial specifications and obtaining the final physical dimensions of the structure. Following the technique here shown, each filter is synthesized taking into account for the loading effects of the whole mani-fold; the filters dimensioning can be carried out with the filters separated from the multi-plexer. In this way the optimization tasks are greatly simplified as compared with previous techniques for multiplexer design. The measured results of a manufactured prototype show return losses under 17 dB and minimum isolation between channels equal to 25 dB. [ABSTRACT FROM AUTHOR]

In this article, we present two methods to de-embed the filters' responses from a diplexer whose junction is known. A weak identification problem is here described by means of a dual-state junction and can be applied for general diagnosis of prototype diplexers. A strong identification problem based on rationality of the filters is also introduced here and is suited for a real-time tuning process. This technique is based on a polynomial approximation derived analytically from the algebraic structure of the diplexer's response. Additional unknown delays violating the rational assumption can be moreover detected and estimated. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013. [ABSTRACT FROM AUTHOR]

An error envelope feedback linearizer (EEFL) employs the complex envelope of the distortion generated by the power amplifier (PA) as a feedback to control the envelope of the PA input signal; in this way, a sort of predistortion is realized, allowing the reduction of the intermodulation distortion (IMD) produced by the PA. A recently introduced EEFL architecture is investigated in this article from a mathematical point of view; starting from the functional scheme of the linearizer, its response to one- and two-tone excitations is evaluated, allowing a simple estimation of the achievable performances (IMD reduction). The stability issue may constitute a severe limitation for this class of linearizers; by using both the introduced mathematical model and numerical simulations, the stability is investigated in order to obtain better insight into the working mechanism of the EEFL. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006. [ABSTRACT FROM AUTHOR]