1. Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities
- Author
-
Seung-Kil Lim, Jae-Gon Kim, and Hwa-Joong Kim
- Subjects
Engineering ,business.industry ,Strategy and Management ,Process (computing) ,ComputerApplications_COMPUTERSINOTHERSYSTEMS ,Management Science and Operations Research ,Industrial and Manufacturing Engineering ,Reliability engineering ,Wafer fabrication ,symbols.namesake ,Lagrangian relaxation ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,symbols ,Wafer ,Point (geometry) ,Sensitivity (control systems) ,Greedy algorithm ,business ,Decision model - Abstract
In semiconductor wafer fabrication facilities, order-lot pegging is the process of assigning wafer lots to orders and meeting the due dates of orders is considered one of the most important operational issues. In many cases of order-lot pegging, some orders cannot be fulfilled with the current wafers in the lots being processed, necessitating the release of additional new wafer lots into the wafer fabrication facility. In this paper, we propose a simultaneous decision model for order-lot pegging and wafer release planning in semiconductor wafer fabrication facilities, and develop a Lagrangian heuristic for solving the model. The results of computational experiments conducted using randomly generated problem instances that mimic actual field data from a Korea semiconductor wafer fabrication facility indicate that the performance of the Lagrangian heuristic is superior to that of a practical greedy algorithm for practical-sized problem instances. The results also point to how sensitivity analysis can be use...
- Published
- 2014