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This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system.

This article proposes a time-delay digital tanlock loop (TDTL), which uses a new phase detector (PD) design that is optimised for noise reduction making it amenable for applications that require wide lock range without sacrificing the level of noise immunity. The proposed system uses an improved phase detector design which uses two phase detectors; one PD is used to optimise the noise immunity whilst the other is used to control the acquisition time of the TDTL system. Using the modified phase detector it is possible to reduce the second- and higher-order harmonics by at least 50% compared with the conventional TDTL system. The proposed system was simulated and tested using MATLAB/Simulink using frequency step inputs and inputs corrupted with varying levels of harmonic distortion. A hardware prototype of the system was implemented using a field programmable gate array (FPGA). The practical and simulation results indicate considerable improvement in the noise performance of the proposed system over the con...

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35 µm CMOS process with a 3.3 V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.

This article describes the design, simulation, implementation and testing of a novel low-cost multiple-range programmable digital phase detector. The detector receives two periodic signals and calculates the ratio of the time difference to the time period to measure and display the phase difference. The resulting output values are in integer form ranging from −180° to 180°. Users can select the detector pre-set operation frequency ranges using a three-bit pre-scalar. This enables to use the detector for various applications. The proposed detector can be programmed over a frequency range of 10 Hz to 25 kHz by configuring its clock divider circuit. Detector simulations were conducted and verified using ModelSim and the design was implemented and tested using an Altera Cyclone II field-programmable gate array board. Both the simulation and actual circuit testing results showed that the phase detector has a magnitude of error of only 1°. The detector is ideal for applications such as power factor measurement ...

A fully digital phase tracking loop based on a phase frequency detector and a digitally control phase shifter has been proposed to extract the continuous carrier signal from the burst-like input signal, whose frequency is very close to or same as that of the frequency of the local oscillator used in the loop. The phase drift of the loop is negligible during the off interval of the input signal. This property makes it useful in synchronising bursty signals. The performance of the proposed system has been verified through hardware experiment.

An efficient architecture for a low jitter all digital phase locked loop (ADPLL) suitable for high speed system-on-chip (SoC) applications is presented in this article. The ADPLL is designed using standard cells and described by hardware description language. The ADPLL implemented in a 90-nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that the PLL has a cycle to cycle jitter of 164 ps at 100 MHz. Because the digitally controlled oscillator can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for SoC applications.

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.

A novel indirect frequency synthesizer (FS) circuit comprising a multiplexer (MUX) controlled ring oscillator (RO) and a Hogge phase detector has been proposed. The circuit will synthesize signals having better spectral purity and will consume less power compared to conventional indirect FS circuits. The MUX controlled RO will provide higher flexibility in frequency control and the voltage controlled oscillator (VCO) sensitivity can be varied easily to keep loop gain fixed for different values of synthesized signal frequencies. Hardware experimental results have been given to establish theoretical anticipations.

A new phase detector method which can detect the phase difference between two sinusoidal signals in one-fourth of a cycle is proposed. The phase difference is represented as a dc output voltage, and it can distinguish phase leading or phase lagging by using voltage polarity. Since no low-pass filter is used, its detection time is not more than one-fourth of a cycle. The detection time performance is superior to that of conventional phase detectors.

A new phase detector that can measure the phase difference of sinusoidal or square wave signals and represent it as a DC output voltage is proposed. The proposed detector can distinguish phase leading or phase lagging by using output voltage polarity. This detector is implemented by an analogue electronic circuit without using the low-pass filter, and its detection lime is not more than a half-cycle. This performance is superior to conventional phase detectors. Additionally, its linear characteristic is good.

The performance of a linear phase detector for variable phase in the presence of noise is investigated. Measurements of the total phase (range increase) are possible by employing this phase detector. An algorithm of such measurements is formulated. The Kalman filter is used in the final estimation of the position.

A new phase-frequency detector that gives a DC output voltage proportional to the phase difference of the input signals is described. A linear, time-discrete, phase difference to voltage converter, followed by a holding circuit, is used to replace the conventional phase detector and lowpass filter. The circuit has been tested in a PLL motor control system. Test results indicated a definite improvement in system performance. The circuit of the detector and its model are presented.

The possibility of using a costas loop for the carrier regeneration in tamed frequency modulation (TFM) signal is investigated. By first setting up all important phase changing rules and suitably classifying the various possible phase paths, the equivalent phase detector characteristics (for TFM signal input) of the four phase costas loop are derived. Performance degradation, when compared with the same loop for QPSK. signal input, is also pointed out and discussed.

In this paper we study the non-linear response of phase-locked loops (PPL's) in the presence of an FM signal and an interfering carrier. The additional sinusoidal component has a non-commensurate frequency relationship with the fundamental. A two sinusoidal input describing function (TSIDF) technique is employed to solve the problem. Analytical expressions are derived for the steady-state dynamic phase error response of the system to the FM signal and interfering carrier. The effect of the interfering carrier on the FM/PM frequency response of the PLL is demonstrated by means of frequency response plots. Since the method of approach is general with respect to the signal conditions, loop filter and phase detector, the response of PLL's to an FM signal, which is a particular case of the above problem, is also analysed in this paper. Results are presented for a sinusoidal phase-locked loop with (a) RC loop filter and (b) perfect integrating filter.

A new phase-comparator using bucket brigade device (BBD) is proposed. It is composed of a conventional phase-comparator with a phase shifter using BBD in the feedback path. Its dynamic range is wider than that of the conventional phase-comparator. This phase-comparator will find many applications, such as a demodulator for the widely phase-modulated wave and a component for PLL.

A theoretical and experimental study of the phase-locked regulator system with separately excited DC motor and triangular phase comparator (EXOR gate, over-driven Gilbert multiplier) is presented in this paper. A new model for the triangular phase comparator is proposed which results in a closed expression that estimates the capture range and shows the effect of the encoder resolution on system performance. Stability conditions and certain design criteria are also given. Finally it is concluded that the PLRS cannot operate at low speeds and its speed range is just, a portion of the motor speed range.

The acquisition problem of a phase locked loop used in tracking a very short pulses considered. The short, duration of these incoming pulses combined with the requirement of improving noise performance, motivate the use of special wave forms such that the system is exposed to the input signal and noise in the vicinity of the pulse appearing times only. This is done by suitably gating the phase detector. Assuming the width of the pulse is small compared to the exposing time, a recursive equation is derived that enables the calculation of the lock-in and pull-in times. This is then generalized to eater to any value of the input pulse width and a computer program is suggested for computing the lock-in and pull-in times.