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Electronic circuits must address electromagnetic interference due to high-speed transmissions and simultaneous switching actions. This paper proposes a design of novel planar EBG structure L Bridge with embedded slit type with 3 × 3 array fashion, which can be used in a plane layer of a printed circuit board to reduce simultaneous switching noise (SSN). Two sets of pattern such as alternate structure and entire embedded pattern are considered and measured the cut-off frequencies. The performance of the structure is simulated, experimentally verified using R&S®ZVH Vector Network Analyser for the frequency range 0.1 to 10 GHz and compared the outcomes. It is observed that for the −50 dB of noise depth, proposed structure is achieved 1.6 GHz to 10 GHz as lower and upper cut-off frequency. In addition, this concluded the noise suppression using equivalent circuit model and parallel plate wave guide theory. Signal integrity on this structure is also analysed with single-ended and differential mode signal transition. Eye pattern is generated and compared for measuring and validating the signal quality while using this EBG structure. [ABSTRACT FROM AUTHOR]

Memristor-based combinational logic is one of the unique concepts of designing digital circuits to achieve compact design, faster operation, and lesser power consumption. This work presents a unique memristor-based transistor-less combinational logic circuits design and analyses the performance benchmarking with other state of the art methods. Observed results demonstrated that the proposed design performs comparatively well in terms of size, speed, and power consumption. Basic combinational logic circuits, such as full adder, multiplexer, decoder, and priority encoder are being designed using the University of Michigan Model. The basic logic gates which include AND, OR, XOR are also designed using the concept of memristor ratioed logic. The proposed design of full adder utilises 14 memristors and 2 inverters, the delay time is 26.5ps, and power consumption is 0.5nW which is less compared to the other design. The proposed 4 × 1 multiplexer, 2-to-4 decoder and 4-to-2 priority encoder consume 0.6nW, 0.15nW, and 0.87nW power respectively. The observed improvement in these significant parameters demonstrates the potential of using memristor-based transistor-less combinational logic circuits in modern electronic devices. [ABSTRACT FROM AUTHOR]

In this paper, a synchronous reference frame (SRF) method based on a modified phase lock loop (PLL) circuit is developed for a three-phase four-wire shunt hybrid active power filter (APF). Its performance is analysed under unbalanced grid conditions. The dominant lower order harmonics as well as reactive power can be compensated by the passive elements, whereas the active part mitigates the remaining distortions and improves the power quality. As different control methods show contradictory performance, fuzzy logic controller is considered here for DC-link voltage regulation of the inverter. Extensive simulations of the proposed technique are carried out in a MATLAB-SIMULINK environment. A laboratory prototype has been built on dSPACE1104 platform to verify the feasibility of the suggested SHAPF controller. The simulation and experimental results validate the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

In this paper, a function is defined to be strictly stable if all the zeros and poles of the function are in the open left half-plane. Although many omittance circuits employing CCIIs are known in the literature, this paper proposes methods for synthesizing any floating linear time-invariant one-port with given real, rational, strictly stable driving-point immittances and any real, rational, strictly stable, z and y parameters of multiports with CCII--, even if the parameters are mutually independent. A minimum number of CCII-- are used to achieve our object. [ABSTRACT FROM AUTHOR]

In this paper we investigate the multi-stable transistor circuits of which basic operation can be regarded as threshold logic. The sensitivity analysis on the actual circuits is also considered as well as their logical behaviour.
The multi-stable circuits are usually constructed from the flip-flop circuits which have basically two transistors. The transistor, however, can be regarded as a comparator whose output ('0' or '1') depends on whether the input level is higher than a reference (including the insensitive region) or not. Hence, combining it with an adder circuit, each input of which is multiplied by some factor, the circuit operates as a threshold device (Hampel and Winder 1971).
In this paper we investigate these problems and suggest that the network constructed from n threshold devices is useful only as an n-stable circuit. [ABSTRACT FROM AUTHOR]

This paper considers the linearisation of an asymmetrical two-way Doherty amplifier by the method that uses the second harmonics and fourth-order non-linear signals for linearisation. These even-order signals for linearisation are extracted at the output of the peaking amplifier, adjusted in amplitude and phase and injected at the input and output of the carrier amplifier transistor in the Doherty configuration. The effect of linearisation has been experimentally confirmed on a fabricated asymmetrical Doherty amplifier with the additional circuit for linearisation. The suppression of the third-order intermodulation products has been carried out for two-tone test, 64QAM and WCDMA digitally modulated signals in a range of signal power. [ABSTRACT FROM AUTHOR]

Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm2 and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits. [ABSTRACT FROM AUTHOR]

This paper presents threshold comparison operation, transmission operation and union operation which can be used to describe the function of MOS transistors in a pass-transistor network. The relative properties and circuit realizations of these operations, and the transmission function expression by use of these operations are discussed. A transmission function theory suitable to CMOS network synthesis is proposed. This paper also discusses the simplification of ternary functions and proposes minimized design of some basic ternary CMOS circuits. The computer simulation using SPICE2G5 has confirmed that these circuits have desirable DC transfer characteristics. [ABSTRACT FROM AUTHOR]

The paper presents a simulation program (CADLEM) to analyse electronic circuits including non-linear elements such as diodes, bipolar transistors, MOSFETs, operational amplifiers and thyristors. The computational techniques and the components are briefly described. The paper shows several examples, illustrating the capabilities of CADLEM. [ABSTRACT FROM AUTHOR]

In this paper Chua's method of realizing strictly unicursal driving point (DP) characteristics is extended to encompass the synthesis of a class of non-strictly unicursal DP plots. It is shown that such DP plots can be decomposed into the sum of two or more strictly unicursal curves and their corresponding realizations can be connected together in series and/or parallel to form the desired non-strictly unicursal curve. [ABSTRACT FROM AUTHOR]

The realization of special types of the generalized-immittance converters will be given here using the second-generation current conveyor. Of particular interest in this paper is the new realization of the voltage generalized-immittance converter having conversion immittance function proportional to s. It will be seen that two realizations exist for each converter.
A special type of the current generalized-immittance converter was recently introduced, and used in one of the recent and most attractive RC active network synthesis procedures (Antoniou 1970). Antoniou (1970) used the operational amplifier as the active building block in the realization of the current generalized-immittance converter.
In a recent publication, Sedra and Smith (1970) introduced the second-generation current conveyor (will be abbreviated here as the current conveyor CC) and used it in the realization of some active network elements. The current conveyor is a versatile building block, as it can be used as a current summer, current differentiator, current integrator, current amplifier, etc.
In this paper the simulation of special types of both voltage and current generalized-immittance converters using the current conveyor will be given. [ABSTRACT FROM AUTHOR]

This paper presents a three-electrode potentiostat transducer circuit for electrochemical sensing system designed for biomolecular detection. Melatonin has been found to be used as a significant index of potential breast cancer risk. The proposed chip automatically measures the redox current which depends on the concentration of melatonin in the analyte solution. Moreover, a current-to-time converter is designed to convert the sensed current into the proportional digitized time signal for back-end signal processing. Cyclic voltammetry and molecularly imprinted polymers were used in the experiments. The sensing electrodes were coated with a thin film imprinted with the target molecule. Fabricated in the TSMC CMOS 0.18 μm 1P6M technology, the proposed chip has a core chip size of 0.083 mm2 and a power consumption of 1.143 mW with a 1.8 V supply voltage. This chip can measure the sensed current from ±15 to ±1500 µA with a linearity of R2 = 0.999. In the cyclic voltammetry measurement, this chip has an error of less than 0.7%. The urine measurement results of the proposed chip were compared with that of enzyme-linked immune sorbent assay. Verified by melatonin concentration measurement, the proposed chip with high sensitivity demonstrates the feasibility of melatonin concentration detection, which contributes to the examination of breast cancer. [ABSTRACT FROM AUTHOR]

A high-accuracy resolver-to-linear signal converter for the measurement of angular displacement is proposed in this paper. The proposed converter comprises two sections: a demodulator and linear shaper. In the first section, the demodulator makes use of the sample-and-hold circuit (SHC) to sample the peak amplitude of the resolver signal. The control signal of the SHC is provided from the resolver signals instead of the excitation signal used in traditional approaches. The proposed demodulator requires no analogue multiplier and low-pass filter. Therefore, the fast response time of the proposed demodulator is achieved. In the second section, the linear shaper consists of the inverse-sine function scheme together with a switched-gain amplifier to produce the linear signal proportional to the shaft angle. The hyperbolic tangent characteristic of the operational transconductance amplifier is utilised to realise the inverse-sine function scheme. The proposed technique requires one phase of the resolver signal to obtain the linear signal. Therefore, the position error caused by amplitude imbalance between the two resolver signals is avoided. The performances of the proposed converter are discussed in detail and demonstrated by an experimental implementation using commercial devices. The experimental results show that the maximum relative error and response time for the excitation frequency of 3 kHz are measured as 0.06% and 0.11 ms, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a novel implementation of switched capacitor (SC) fractional order differentiators (FOD) based on Tustin operator and Al-Alaoui operator. The existing models of half differentiator s1/2 have been expanded using continued fraction expansion and implemented using PSpice. The PSpice simulation results are compared with the theoretical results in the continuous time domain. The results validate the effectiveness of the SC circuit implementation of the proposed approach. A detailed analysis of the influence of the non-idealities of the third order Al-Alaoui operator based half differentiator is performed. The analytical expressions for errors in magnitude and phase due to the above mentioned non-idealities have been derived for the SC integrator and amplifier circuits used in our realisation. [ABSTRACT FROM AUTHOR]

This paper provides a new method to determine the equivalent circuit parameters for a two ?/2 resonators filter structure. The method combines the direct parameter-extraction technique and optimization method. Both the extrinsic and intrinsic parameters in the equivalent circuit are determined at low frequency by using the de-embedding technique as the initial values for optimization. The calculated frequency response of the equivalent circuit model for the structure agrees well with the measured results both in magnitude and phase. [ABSTRACT FROM AUTHOR]

Power electronics is an emerging technology. New power circuits are invented and have to be introduced into the power electronics curriculum. One of the interesting new circuits is the matrix converter (MC), and this paper analyses its working principles. A simple model is proposed to represent the power circuit, including the input filter. The power semiconductors are modelled as ideal bidirectional switches and the MC is controlled using a direct transfer function approach. The modulation strategy of the converter is explained in a complete and clear form. The commutation problem of two switches and the generation of overvoltages are clarified. The paper also includes a soft-switching commutation method that allows for a safe commutation of the switches. Finally a complete simulation scheme, using Matlab®-Simulink®, is discussed. [ABSTRACT FROM AUTHOR]

This paper presents a floating-body charge monitoring technique, which does not require the use of body contacts on the device being monitored. A charge monitor is placed along side with the circuit that is susceptible to the floating-body effects in partially depleted (PD) SOI CMOS circuits. It mimics the circuit topology and operating history of a concerned circuit, specifically the worst-case body voltage of the critical device(s) under consideration. The monitoring is achieved by intentionally triggering a parasitic bipolar current pulse and setting the a state recording latch, which subsequently activates the speed recovering circuitry that compensates the loss of performance at critical circuit nets due to the presence of parasitic bipolar current. Implementation examples are given and described. This technique restores performance and improves timing robustness of the MUX-type and SRAM bit line circuits by minimizing the delay degradation or variation from parasitic bipolar currents. [ABSTRACT FROM AUTHOR]

This paper describes the construction of new circuit configurations for some sequential circuits. These circuits are based on the microthyristor as a microelectronic bistable device that can store logic one and logic zero and on NMOS transistors that act either as pass transistors or drivers. The shift register, considered as a main type of sequential circuit, is developed from a D flip-flop that is designed basically from the microthyristor as a bistable device. Moreover, different types of counters based on the microthyristor as a storing element are developed. Microthyristor sequential circuits were found to perform well. [ABSTRACT FROM AUTHOR]

The objective of this paper is to introduce new useful theorems relating to port interchange in current mode current conveyor circuits. Several applications of the theorems are given, among which a new current mode notch and all-pass filter with complex poles is generated from a known circuit with real axis poles, based on the interchange of the input and ground theorem. PSpice simulations are included. [ABSTRACT FROM AUTHOR]

A matrix method for the detection of static hazards in combinational logic circuits has been reported (Heal and Page 1993). The method generates 0 and 1-sets of all nodes in each gate level of a circuit progressively until it reaches the output of the circuit. The sets generated are subsequently used to determine the existence of static hazards. This paper introduces enhancements to improve the capabilities and performances of the method, which is applicable to the detection of logic hazards in synchronous combinational logic circuits only. It is shown how certain matrix operations can be simplified to save storage and computation time. A simpler way of determining static hazards is proposed. Required modifications of the method to incorporate the detection of dynamic hazards are presented. It is further shown that the algorithm can also be applied to the transient analysis of digital circuits with exclusive-OR (EX-OR) gates. Examples are given for illustration. [ABSTRACT FROM AUTHOR]

New and natural proof are proposed for both the arcsine law and a related result. Both results are of extreme practical importance. The arcsine law and its related result naturally emerge when studied against their most natural backdrop provided by a detailed multi-bit quantization, already carried out in a multi-dimensional (m-D) setting. We also show that amongst the whole class of 1-bit uniform quantizers treated in this paper, the only practically-useful member for which both the arcsine law and its related result hold is the mid-riser (i.e. with no dead zone) type of quantizer, upon which the well-known relay and polarity coincidence correlators are based. [ABSTRACT FROM AUTHOR]

In this paper we utilize an algorithm (Chiang and Vranesic 1983) to test for the classical stuck-at-fault nodes in CMOS transistor level circuits. The original algorithm may incorrectly produce input test patterns. In this paper we suggest a modification to rectify the algorithm. We demonstrate the testing of stuck-at-faults using our modified algorithm in addition to testing of transistors open/short faults. A complete test set for a fault is defined as the set of all input patterns that can detect that fault. Our modified algorithm differs from the original algorithm in that it produces the complete test set for each possible fault. The original algorithm stops searching once it reaches a test set capable of testing all faults. The set which is produced is not guaranteed to be neither complete nor minimal. Finally the paper introduces some programming techniques used in implementing the algorithm. [ABSTRACT FROM AUTHOR]

In this paper a computer method for fault detection using Boolean matrices has been proposed. The method is computationally advantageous and it also defines the normal output of the circuit for all stuck-line faults. A computer program using Fortran IV, which is successfully tried on TDC-316 computer is also given. An example illustrates the method. [ABSTRACT FROM AUTHOR]

In this paper, a new approach in identifying chaotic behaviour of nonlinear circuits is presented. This approach could be very useful to circuit designers, whether they pursue a chaotic behaviour or not. Simulation tools used for radio-frequency circuit design (Cadence SpectreRF), initially developed to characterise harmonic oscillators, are now utilised to detect chaotic behaviour, as well as routes to chaotic mode of operation. Specifically,Periodic Steady State Convergence Normis used for the first time for chaos detection in circuits. The advantages of this method (especially in terms of simulation time) are presented, together with an example of detection of chaotic route to chaos in the case of a chaotic-operatingColpittsoscillator. [ABSTRACT FROM AUTHOR]

In this paper, we present a systematic method for designing single error correcting (SEC) and double error detecting finite field (Galois field) multipliers over GF(2m). The detection and correction are done on-line. We use multiple Parity Predictions to detect and correct errors. Specifically, a structural approach is first presented. The predicted parity bits are derived from the primitive polynomials for generating the fields. Further, a hybrid approach is presented where the multipliers and PP circuits are synthesised, and the decoding and correction circuits are structurally combined to form the complete error correcting designs. Although the article considers only a finite field multiplier, without loss of generality, the technique could be applied to any combinational logic circuit. Our technique, when compared with existing techniques, gives better performance. We show that our SEC multipliers over GF(2m) require about 100% extra hardware, whereas with the traditional SEC techniques, such as the triple-modular redundancy (TMR), this figure is more than 200%. Moreover, the multiple bit error detection and correction using multiple Hamming code were also introduced. [ABSTRACT FROM AUTHOR]

Relatively high transconductance in bipolar devices contributes to the economy of power dissipation on analog integrated circuits. Recently, a high-speed transistor, such as the HBT attracts attention of researchers and developers in electronic communication industries and is expected to be applied to RF circuits. In this paper, high-efficiency bipolar transconductors are presented. The proposed circuits are composed of a hyperbolic function circuit with an intermediate voltage terminal and a triple-tail cell. The parameter values for linearisation are all integers. The values can be realised precisely. The linearity of the proposed transconductors is superior to the triple-tail cell. The linear input range is 1.5 times as wide as that of the conventional triple-tail cell. Nevertheless, the power dissipation is lower than the triple-tail cell. Further, sensitivity analysis shows that the proposed transconductors have lower sensitivity than the triple-tail cell. These properties are confirmed by SPICE simulation. [ABSTRACT FROM AUTHOR]

A novel method for fault diagnosis of analog circuits with tolerance based on wavelet packet (WP) decomposition and probabilistic neural networks using genetic algorithm (GPNN) is proposed in this paper. The fault feature vectors are extracted after feasible domains on the basis of WP decomposition of responses of a circuit being solved. Then by fusing various uncertain factors into probabilistic operations, GPNN methods to diagnose faults are proposed whose parameters and structure obtained form genetic optimisations resulting in best detection of faults. Finally, simulations indicated that GPNN classifiers are correct 7% more than BPNN of the test data associated with our sample circuits. [ABSTRACT FROM AUTHOR]

This paper offers a fresh look into the temperature behaviour and compensation of Schottky barrier diode's radio frequency (RF) resistance. RF resistance of a Schottky diode varies with temperature at conventional fixed current bias as well as fixed voltage bias condition. Here we have proposed “optimum load-line biasing technique” to achieve temperature invariant RF performance of the Schottky diode based RF circuits. Mathematically we have shown and verified by measurements that the proposed technique provides temperature insensitive RF performance over a very wide range of operating temperature. Thus, without any separate temperature sensor and compensation circuits, as used in conventional temperature-compensation schemes, it is possible to achieve temperature invariant RF performance of the Schottky diode based RF circuits. [ABSTRACT FROM AUTHOR]

The demonstration of NOT and OR logic gates using magnetic domain walls could suggest that digital circuit design methodology may apply directly to this new technology to build complex circuits. This paper shows that the use of an external rotating field which propagates domain walls of opposite magnetization in antiphase instants, reveals unforeseen delays which modify the operation of sequential logic circuits. To overcome this difficulty and to introduce a design methodology, a new device capable of re-synchronizing the signals is presented. [ABSTRACT FROM AUTHOR]

A high-performance current-mode instrumentation amplifier circuit is described in this paper. It has a high common mode rejection ratio, high gain, high accuracy, wide bandwidth and bandwidth gain-independence. It utilizes commercially available integrated circuits and is easily implemented. Experimental results show that at low frequencies a common mode rejection ratio of 120 dB is attainable. [ABSTRACT FROM AUTHOR]

This paper presents two current-mode all-pass sections, employing only grounded components, which is important from the integrated circuit (IC) implementation point of view. The use of the grounded capacitor allows the IC implementation with standard CMOS technologies. The circuits can be made electronically tunable due to grounded resistors that can be realized by using voltage controlled MOS based resistors. In addition, the circuits have both low input impedance and high output impedance for easy cascadability. The stability analysis proves that the circuits are stable. SPICE simulations and experimental results are in close agreement with the theory. [ABSTRACT FROM AUTHOR]

This paper presents three first order resistorless all-pass filters using combinations of current controlled current conveyors (CCCII) and a unity gain buffer. All circuits feature single element tuning, low sensitivities, and low output impedances, therefore they are suitable for cascading. Circuit simulation results are found in good agreement with theoretical analysis. [ABSTRACT FROM AUTHOR]

In continuation to our published work (Kosta et al . 2003, 2004a, b) on biological electronic circuits and recently submitted research work Kosta et al . (2005a, b) on natural soil (earth) electronic circuits in this paper we present successful experimental studies which scientifically predicated and established a soil (earth) electronic diode possessing conventional diode characteristics. Experimental lay out, schematic diagrams, tables and graphs are presented. Emergence of soil electronic circuit technology is forecast. [ABSTRACT FROM AUTHOR]

This paper reports three multi-function filters each of which realizes at least three basic functions without any external passive elements. Depending on the circuit, from one to four operational transconductance amplifiers (OTAs), and two operational amplifiers (OPAMPs) are employed. All three circuits are transimpedance-mode circuits; one of them can also operate as a current-mode filter. Therefore this filter represents a dual-mode, multifunction filter. The presented theory is verified with macro models in simulation program with integrated circuit emphasis (SPICE) simulations and post layout simulations, which are carried out with parasitics extracted from the layouts of the filter chips. [ABSTRACT FROM AUTHOR]

Variable delay elements are often used in different types of high-speed integrated circuits, mainly intended for delay compensation, skew equalization, etc. These circuits are normally realized as hybrid, composed of digital and analog controlled parts. The digital part is used for coarse-grain, while the analog for fine-grain delay variation. Efficient analog delay element architecture is proposed in this paper. The proposal is based on modification of the standard current starved delay element solution. An analytical equation that corresponds to the delay of the circuit is given also. In terms of control voltage, the proposed circuit has a linear delay transfer function in the whole range of regulation. Improvement is achieved at a cost of small hardware overhead in respect to the standard solution. Delay linearity error is less than 1% and the agreement between analytical model and simulation results is good, i.e. the error is less than 5%. [ABSTRACT FROM AUTHOR]

This paper describes a high frequency and high precision full-wave rectifier using a fully differential input and output operational transconductance amplifier (FDIO-OTA), which is very suitable for CMOS technology implementation. The system comprises a voltage to current converter, precision full-wave rectifier and a current-to-voltage converter. An input voltage signal is converted into two symmetrical current signals by using a FDIO-OTA. Two current signals will be rectified by using MOS diodes and convert into output voltage by using grounded MOS resistor. The circuit exhibits a very precise rectifier and very high operating frequency. The simulation results demonstrate the performance of the proposed circuit. [ABSTRACT FROM AUTHOR]

This paper describes the design of an AC–AC converter capable of generating a high-quality output. It is based on the Cuk configuration, with the transistors replaced by bidirectional switches. Since there are no transformers in the configuration, the converter lends itself to a compact and lightweight implementation. The design process is aimed at using, as much as possible, the tools and devices already developed for DC–DC applications. This approach greatly simplifies the design and implementation of the converter. An integrated circuit, developed for DC–DC applications, is used to control the converter. Both the set-point and the feedback signal are rectified in order to fit the input range of the controller. Tests performed show that the output exhibits a maximum total harmonic distortion of 3% (resistive load). The efficiency is slightly higher than 89%, and the average output regulation is 0.3%. The converter is capable of correcting voltage sags down to 60% and voltage swells up to 30%, with the output returning to its nominal value within one mains cycle. The results show that the converter is suitable for energizing information-processing equipment. [ABSTRACT FROM AUTHOR]

This paper presents a realization of voltage-mode and current-mode active-only biquad circuits with a two-integrator loop-structure. The circuits are constructed solely with operational amplifiers (OAs) and operational transconductance amplifiers (OTAs). The biquad circuits can realize the multiple circuit transfer functions, and the circuit parameters can be tuned orthogonally through adjusting the transconductance gains of the OTAs. Also, these biquad circuits enjoy very low sensitivities with respect to the circuit active elements. Some examples are given together with simulated results by PSPICE. The circuit configurations are very suitable for implementation on both bipolar and CMOS technologies. [ABSTRACT FROM AUTHOR]

Polycrystalline silicon (poly-Si) thin .lm transistor (TFT) technology is very suitable for driving an active matrix LCD (AMLCD) panel as the driver circuit, and the panel can be integrated on the same substrate. This allows the entire display system to be thin and makes the concepts of 'TV on wall' and 'sheet computer' possible. However, the large variation of threshold voltage of poly-Si TFT across the wafer makes it difficult to obtain analogue amplifiers with constant gain and phase margin. In this paper, an analogue data driver for the poly-Si TFT AMLCD is proposed. An operational amplifier with a gate bias-voltage generation circuit for this analogue data driver, with characteristics independent of variations in threshold voltage, will be presented. In Hspice simulation, with threshold voltage varying from 2.5 V to 4.5 V, gain variations of the proposed amplifier were reduced from ±10 dB to ±0.2 dB and phase margin variations were reduced from 10° to 0.37° compared with typical operational amplifier design. This enables the analogue data driver for AMLCD to be implemented in poly-Si TFT technology. [ABSTRACT FROM AUTHOR]

Because of their several advantages over the traditional voltage mode op-amp, current feedback op-amps (CFOAs) have attracted prominent attention as alternative building blocks for biquad filter realization. Previously known universal current mode (CM) biquads (i.e. those capable of realizing all five generic filter functions, namely low-pass, band-pass, high-pass, notch and all-pass) are realizable with CFOAs but require two to nine CFOAs. Although a few dual-function/three-function single-CFOA-based CM circuits have appeared in the literature, no single-CFOA-based canonic universal CM biquad with explicit CM output has been reported until now. This paper presents such a circuit. The workability of the proposed circuit has been confirmed by PSPICE simulations based upon AD844-type CFOAs. [ABSTRACT FROM AUTHOR]

This paper describes the development of new configurations for flip-flops which are based on a microthyristor as a storage element, the NMOS transistor as a series switch or a driver and a high pull-up resistor. The performance of these flip-flops is analysed, using a PSPICE simulator. These devices perform well with regard to speed and power consumption and are more compact because of the use of the microthyrister. [ABSTRACT FROM AUTHOR]

This paper investigates in detail the basic mechanisms of hysteretic delay and noise margin variations for floating-body partially depleted SOI CMOS domino circuits. We first consider the 'clock cycling scenario', which completely eliminates (or isolates) the hysteresis effect of the output inverter, thus allowing one to observe and understand the hysteresis effect of the front-end domino logic stage. Three cases, based on whether the input signals are domino input signals, from other domino circuits, static input signals, from static circuits or latches; or a combination of domino and static input signals, are examined and differentiated. It is shown that hysteretic delay variation is the largest and the noise margin worst for the case with mixed domino and static input signals. Although the delay and noise margin disparities among the three types of input signals are significant at the beginning of the clock cycles, they converge as the circuit approaches steady state. The 'data cycling scenario' with the combined hysteresis effect of both the front-end domino logic stage and the output inverter is then discussed. Circuits operating under the 'data cycling scenario' are shown to have less body charge loss through the switching cycles than under the 'clock cycling scenario'. [ABSTRACT FROM AUTHOR]

Realization of RC-active filters, as proposed by Sallen and Key, consists of cascade connection of suitable second- and first-order building blocks. The paper presents design tables for two active RC circuits realizing low-pass polyonimic filters. The functions realized are of second to eighth-order low-pass Butterworth, Chebyshev (with 0.1, 0.5, 1, 2 and 3 dB ripple) and Bessel variety. This method uses simple op-amp integrator blocks and can equally be applied to both continuous-time and switch-capacitor filter designs. The advantages of this method are: simple method of designing LP filters from second to eighth order using integrator blocks (e.g. MAX 274 and MAX 275); low sensitivity to component values; low spread in component values; good tuning; can tune parameter f 1 (cutoff frequency). The disadvantages of this method are: no independent adjustment of the cutoff frequency and the Q -factor; fixed gain of unity. [ABSTRACT FROM AUTHOR]

In the present paper the analysis of a gap-coupled microstrip antenna (GCMSA) is carried out using the circuit concept and consequently various parameters such as input impedance, VSWR and return-loss are investigated for different air gap lengths. It is observed that the resonant frequency of the antenna with different substrates depends on the gap length. The gap-coupled antenna behaves as an RL network below the resonant frequency for all substrate materials and gap lengths, whereas the antenna behaviour above resonance is like an RC network. It is further observed that the resonant frequency of the GCMSA decreases with increasing gap length. [ABSTRACT FROM AUTHOR]

Beta basis function neural networks (BBFNNs) are powerful systems for learning and universal approximation. In this paper, we present a hardware implementation of the Beta neuron using the CMOS subthreshold mode. We describe the low power-low voltage analogue Beta neuron circuit. Three main modules are used to realize the electronic Beta function: a logarithmic currentto-voltage converter, a multiplier and an exponential voltage-to-current converter. Simulation results show the validity of our neural hardware implementation. The parameters of the electronic Beta function are controlled independently by current sources. This analogue implementation could be used easily to realize analogue BBFNNs. [ABSTRACT FROM AUTHOR]

A theoretical analysis of a resonant-cap IMPATT oscillator has been performed on the basis of a device-circuit interaction where the resonant-cap is considered as a radial-line cavity around the diode. the theoretically analysed results have been evaluated through computer-aided solutions. It is found that to obtain the optimum performance of the oscillator with a given device there are optimum cap-circuit dimensions, i.e. a ( D-h ) combination for which the load impedance terminating the resonant-cap cavity nearly equals the characteristic impedance of the rectangular waveguide in which the resonant-cap is mounted. Also the theoretical computations show that the ratio of the physical cap diameter ( D ) and cap height ( h ) to the wavelength of oscillation (lambda ) is nearly 0.36 and 0.08, r respectively, while the effective electrical cap radius ( r ) is approximately a eff quarter-wavelength. These results are in good agreement with the previously reported experimentally measured values. the detailed theoretical analysis and the corresponding computed results reported in this paper are expected to be a good basis for the design and understanding of the properties of the cap-type microwave and millimetre-wave sources. [ABSTRACT FROM AUTHOR]

New CMOS transmission gate (TG) fault models are described. The TG is observed as a bilateral logic circuit. Its fault models are obtained using a mathematical circuit analysis of the elementary network and these are verified using the electronic circuit analysis program MOST. Another topic covered by the paper is faulty state propagation through the TG. The results of the research described above enable successful fault simulation of circuits containing transmission gates. [ABSTRACT FROM AUTHOR]

This paper deals with electronic tuning of a 950MHz shielded dielectric resonator by using a varactor-loop circuit. A theoretical investigation based on an accurate model circuit is presented. Phenomena such as jumps in frequency and amplitude, and degradation of the DR qualities are described. [ABSTRACT FROM AUTHOR]

Examines a novel fully differential drift-free switched capacitor filter. Synthesis of the state variable equations; Pass band sensitivities; Advantages of fully differential circuits.

This paper points out that a commercially available dual-operational transconductance amplifier package (CA3280) can be efficiently used as both positive and negative second-generation current conveyors, floating negative impedance converters and floating nonlinear impedance converters. In many situations, no other active devices are required to implement the above circuit functions. [ABSTRACT FROM AUTHOR]