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This paper describes the design of a dynamic voltage restorer (DVR) that can simultaneously protect several sensitive loads from voltage sags in a region of an MV distribution network. A novel reference voltage calculation method based on zero-sequence voltage optimisation is proposed for this DVR to optimise cost-effectiveness in compensation of voltage sags with different characteristics in an ungrounded neutral system. Based on a detailed analysis of the characteristics of voltage sags caused by different types of faults and the effect of the wiring mode of the transformer on these characteristics, the optimisation target of the reference voltage calculation is presented with several constraints. The reference voltages under all types of voltage sags are calculated by optimising the zero-sequence component, which can reduce the degree of swell in the phase-to-ground voltage after compensation to the maximum extent and can improve the symmetry degree of the output voltages of the DVR, thereby effectively increasing the compensation ability. The validity and effectiveness of the proposed method are verified by simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by using T flip-flops. The unwanted triggering action of the master clock to flip-flops can be isolated during T = 0. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit. [ABSTRACT FROM AUTHOR]

Shrinking in the device dimensions increases the device density on the chip and thus reducing the overall chip area requirement for logic implementation. Minimising the chip area is not a lonely optimisation performance factor for a VLSI chip designer. The other equally important performance parameters such that power dissipation and propagation delay are the thinkable facts for a designer. The focusable part of power dissipation is the huge leakage current in deep submicron (DSM) regime. Many leakage reduction techniques are applied to reduce the leakage current in the DSM regime but they have own limitations. Our proposed on/off logic (ONOFIC) approach gives an excellent settlement between power dissipation and propagation delay for designing the nanoscale CMOS circuits. It uses extra insertion of two transistors (an NMOS and a PMOS) within the logic block. The exact on/off level of the ONOFIC block improves the power dissipation and propagation delay of the logic circuits. In this article, ONOFIC approach is compared with the LECTOR leakage reduction technique and output results show that our proposed approach significantly reduces the power dissipation and enhancing the speed of the logic circuits with superior power-delay product. [ABSTRACT FROM PUBLISHER]

Compact physical models are presented for on-chip double-sided shielded transmission lines, which are mainly used for long global interconnects where inductance effects should not be ignored. The models are then used to optimize the width and spacing of long global interconnects with repeater insertion. The impacts of increasing line width and spacing on various performance parameters such as delay, data-flux density, power dissipation and total repeater area are analysed. The product of data-flux density and reciprocal delay per unit length are defined as a figure of merit (FOM). By maximizing the FOM, the optimal width and spacing of shielded RLC global interconnects are obtained for various international technology roadmap for semiconductors (ITRS) technology nodes. [ABSTRACT FROM AUTHOR]

Presents a method for analyzing transmission lines represented by parallel cylinders of unequal radii supporting the TEM mode. Transformation to parallel plate and coaxial configurations; Expression of bilinear transformation in terms of mutually inverse points.

Discusses distributed power systems with direct-current and alternating-current bus architectures. Distribution efficiency; Load regulation characteristics; Power and heat management.