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With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7. [ABSTRACT FROM AUTHOR]

In this paper, seven different MOSFET-C transimpedance filters with their corresponding transfer functions and basic filter specifications, are provided. Presented designs show second-order standard band-pass, low-pass, or high-pass characteristics. Moreover, some filters provide both low-pass and band-pass characteristics. Especially, having a tunability feature makes a design more useful and applicable for various communication and instrumentation systems. The selected filter topology was biased under various biasing conditions to tune central frequency by keeping bandwidth constant. To elaborate the design with different aspects, we checked its small-signal performance by introducing both changing temperature and implementation errors. The theoretical results are in detail verified by numerous simulations using Cadence IC6 Spectre analog design environment. In the design, transistors with 1.8 V supply voltage were used and modelled by the SilTerra Malaysia 180 nm CMOS process parameters. The implemented layout, including metal-insulator-metal on-chip capacitors, occupies an area of 175 μm × 75 μm, while the total power consumption of the filter is found to be only 128.86 μW. [ABSTRACT FROM AUTHOR]

This paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system's front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype's measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm2. The energy required per conversion step is 0.4 pJ/conv. [ABSTRACT FROM AUTHOR]

This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented with 10–40% lesser number of transistors, as compared to the other corresponding circuits available in the literature. The reduction in power and transistor count has been achieved through improved multiplexer designs and judicious use of pass transistor logic. CNFETs have low gate capacitance and hence are ideal devices for ultra-low-power VLSI applications; however, CMOS technology is presently the most preferred technology, because of the easy and low-cost fabrication option made available by the well-established CMOS fabrication labs. Keeping this in view, the proposed mux-based ternary half adder has been designed with both 45 nm MOSFETs and CNFETs. The performance of the proposed HA design has been benchmarked with other CNFET HA reported in the literature. The proposed mux-based CNFET ternary HA, FA and 1-bit multiplier have 10–30% lesser propagation delays than the other designs available in the literature. The reduction in the Power Delay Product (PDP) is 85–99% in the proposed mux-based CNFET ternary circuits as compared to the other benchmarked designs. [ABSTRACT FROM AUTHOR]

In this paper, three novel designs for single-stage, 3-input XOR logic cells are proposed. The design uses either Transmission Gate (TG) or Pass Transistor (PT) on similar topologies. The proposed circuits are area and power efficient because minimum-sized transistors are used in ratioless realisations. At the output, the designs give strong logic-levels. The topologies have minimised delay because the critical path consists of only three minimum-sized transistors. The delay estimation is presented. The circuits are simple and layouts are easy to build. Further, rail-to-rail voltage-swing at the output ensures good driving capability even at low voltages and at high frequencies ranging up to 10 GHz with minimum transistor count. The proposed designs and other existing candidate designs are simulated in a pragmatic condition on Cadence 90 nm CMOS technology at various supply voltages ranging from +0.8 V to +1.2 V. The simulation results illustrate that the proposed designs have comparable delay time to most candidate designs while it outperform all of them on total power consumption and PDP. As expected, the TG-based design reports best performance while the PT-based design follow as closed second with better component economy and control input overload. An application of the proposed XORs in ripple carry adders confirms the functionality of the cells in circuit implementation. [ABSTRACT FROM AUTHOR]

Differential cascoded voltage switch logic (DCVSL) cells are among the best candidates of circuit designers for a wide range of applications due to advantages such as low input capacitance, high switching speed, small area and noise-immunity; nevertheless, a proper model has not yet been developed to analyse them. This paper analyses deep submicron DCVSL cells based on a flexible accuracy-simplicity trade-off including the following key features: (1) the model is capable of producing closed-form expressions with an acceptable accuracy; (2) model equations can be solved numerically to offer higher accuracy; (3) the short-circuit currents occurring in high-low/low-high transitions are accounted in analysis and (4) the changes in the operating modes of transistors during transitions together with an efficient submicron I-V model, which incorporates the most important non-ideal short-channel effects, are considered. The accuracy of the proposed model is validated in IBM 0.13 µm CMOS technology through comparisons with the accurate physically based BSIM3 model. The maximum error caused by analytical solutions is below 10%, while this amount is below 7% for numerical solutions. [ABSTRACT FROM AUTHOR]

In this paper, we present two new logic schemes to implement full adder cell using XOR-XNOR and NOR gates. Gate diffusion input (GDI) and modified GDI (MGDI) cells help to design low power circuits using less number of transistors. In this work, we design two new NOR gates based on MGDI cell. Then, using one of them and MGDI XOR-XNOR gates, two low-power and energy-efficient full adders which also meet full-swing property are proposed. The performance of our new full adders is evaluated and compared with some of the familiar full adders. Post-Layout simulations using Cadence Virtuoso tools in TSMC 0.18 μm CMOS process technology are carried out and the results show almost 24%–56% (22%–55%) and 36%–66% (28%–62%) improvements in the features power consumption and power-delay product (PDP), respectively. Also, full-swing property of our new adders are proved when they are subjected to all possible input combinations and transitions. [ABSTRACT FROM AUTHOR]

This paper deals with the design of a 6-ternary-digit (6-trit) analogue-to-ternary converter (ATC) by employing a 2-trit simultaneous ATC. The circuit used throughout the design is of the Complementary Metal Oxide Semiconductor (C-MOS) type. [ABSTRACT FROM AUTHOR]

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard. [ABSTRACT FROM AUTHOR]

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode. [ABSTRACT FROM AUTHOR]

Gain and offset represent two important measures to determine the accuracy of a comparator. Thus, analysis on these parameters is very important as they offer designers better understanding of the circuit and allow exploring trade-offs during design. In this paper, two methods were presented to derive a set of design equations that describe the gain, sensitivity, offset, and systematic mismatches observed in typical comparator circuits. A three-stage, fast complementary metal-oxide semiconductor (CMOS) comparator structure is analysed and simulated in order to validate the proposed methods. A 0.13 μm CMOS technology is used for simulations with 1.5 V supply voltage. Bisection theorem was used for gain and sensitivity analysis. Simulation results show that high gain improvement can be possible by using the design equations. The input offset voltage, due to mismatch in the width of the metal oxide semiconductor field-effect transistors (MOSFET) (W) and mismatches in the threshold voltages of the N and P type MOSFETs(VTHN, VTHP), is analysed using a proposed balanced method. The same comparator structure is used for the input offset voltage analysis. Simulations show that an offset improvement can be achieved following the design equations found through the proposed method. [ABSTRACT FROM PUBLISHER]

This paper presents dynamic positive feedback source-coupled logic (D-PFSCL) style which is derived from positive feedback source-coupled logic (PFSCL). The proposed logic style uses dynamic current source in contrast to constant current source of PFSCL to attain lower power consumption. Two techniques for D-PFSCL style-based multistage applications are suggested. Several D-PFSCL gates are simulated and compared with the respective PFSCL counterparts through SPICE simulations by using Taiwan semiconductor manufacturing company 0.18 µm CMOS technology parameters. A maximum power reduction of 84% is achieved for D-PFSCL gates. The effect of process variation on the power consumption of the D-PFSCL gates shows a maximum variation factor of 1.5 between the best and the worst cases. [ABSTRACT FROM PUBLISHER]

This paper presents a hardware authentication BLAKE algorithm based on physical unclonable functions (PUFs) in Taiwan Semiconductor Manufacturing Company low-power 65 nm CMOS. To support hardware authentication feature, PUFs have been organised in BLAKE algorithm as the salt value. The trials table method is used to improve the robust of PUFs, resulting in approximately 100% stability against supply voltage variations form 0.7 V to 1.6 V. By discussing the G-function of BLAKE algorithm, the hardware implementation is considered for acceleration, resulting in significant performance improvements. The die occupies 2.62 mm2and operates maximum frequency 1.0 GHz at 1.6 V. Measured results show that PUFs have great random characteristic and the authentication chip dissipates an average power of 91 mW under typical condition at 1.2 V and 780 MHz. In comparison with other works, the PUFs-based BLAKE algorithm has hardware authentication feature and improves throughput about 45%. [ABSTRACT FROM AUTHOR]

This paper provides a novel attempt to evaluate the gate leakage and delay characteristics of CMOS transistors and logic gates with various alternative high-κ gate dielectrics, which are replacing SiO2 in traditional nanoscale MOSFETs. Results have been obtained for both fixed as well as variable loads. The assumption that all gates drive the same load is considered in order to provide a fair comparison of the effect of the variation of design and process parameters, especially that of different high-κ dielectrics on the gate direct tunnelling current and propagation delay. On the other hand, the variable loading effect considers a set of practical loading conditions for the logic gates. An exhaustive comparison of all cases finally presents concluding evidence that the tunnelling current is independent of the loading conditions. On the other hand, there is an increase in the delay as the dielectric constant of the gate material, and consequently the load on the device, increases. Ultimately, this paper presents fast and accurate models for on-the-fly calculation of tunnelling current and delay with the aim of integrating them into design automation tools. [ABSTRACT FROM AUTHOR]

Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm2 and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits. [ABSTRACT FROM AUTHOR]

A universal sensor interfacing circuit is presented in this paper. It is capable of giving a digital output directly proportional to various types of measured quantities, where those measured quantities are proportional to the square root of some other type of quantity. This sensor interfacing circuit is a square-rooting current-to-frequency converter. The design is based on two current-controlled resistors in CMOS technology with bisection of the input voltage used in place of the ordinary resistors within the relaxation oscillator. There is no need for highly stable voltage or current references in the proposed design. The temperature stability of the design is achieved without the need for any specific setting of the process parameters. Experimental results, obtained on a circuit implemented by discrete components, confirm the predictions of the analysis performed. The relative errors are less than 1% for the input current range from 12 µA to 650 µA, and for the output frequency range from 231 Hz to 2.625 kHz. A solution for extending the input current dynamic range is also given in the paper. [ABSTRACT FROM AUTHOR]

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm. [ABSTRACT FROM AUTHOR]

Energy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm2. Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency. [ABSTRACT FROM PUBLISHER]

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes – sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages. [ABSTRACT FROM PUBLISHER]

Logic circuits with transfer characteristics in the form of hysteresis, proposed in the paper, consist of two stages. The input stage is a standard CMOS logic circuit (inverter, NAND or NOR); the output stage is a simple flip-flop. The flip-flop consists of two inverters and one pair of CMOS transistors functioning as a resistor. The positive feedback loop is closed through these transistors. In the paper the most important static parameters and conditions of normal operation arc analysed in detail. [ABSTRACT FROM AUTHOR]

With CMOS process developing, the Static Random Access Memory (SRAM) suffers unavoidable degradation in terms of read and write stabilities. To optimise the memory with conventional 6-T cell in 7-nm process technology, Response Surface Method (RSM) is adopted to get the optimised relationship among the noise margin, the operating temperature, the supply voltage, the unit ratio, the pull-up ratio and the pre-charged voltage, et al. It shows that RSM approach is an effective statistical method for the optimisation of the SRAM cell, especially in the nano-scale scheme. In order to prove the superiority of the RSM approach, the noise margin variation is investigated from 90 nm to 7 nm technology nodes based on the general butterfly curves approach for the comparison. It shows that the stability of the SNM of the 6-T cell tends to be degraded with the continuous shrinkage of the process nodes. The RSM approach is demonstrated to be an effective way for the optimisation of the SRAM cell in single-digit nanometre node. [ABSTRACT FROM AUTHOR]

Leakage current increment is a critical challenge in short channel transistors. In this paper, a new high current performance is presented that not only reduces leakage current but also improves the on-current. The key idea in this work is to modify the doping density with inverted-V shape (IVS) in the vertical direction of the channel. By employing IVS doping density, short channel effects such as drain-induced barrier lowering and threshold voltage roll-off improve and the leakage current significantly reduces compared conventional uniform doping double gate MOSFETs. In this paper, by Conduction band energy modification, in weak inversion regime, high potential height is built that carriers cannot inject in to the channel and reduces leakage current. Furthermore, in strong inversion regime, built-in electric field, leads to better channel carriers’ acceleration and transportation which make on-current improvement. So, the high on–off current ratio (Ion/Ioff) is expected. [ABSTRACT FROM AUTHOR]

In this paper, a multiple-input single-output (MISO) voltage-mode bi-quad active filter using voltage differencing voltage transconductance amplifier (VDVTA) is designed and analysed. The filter can realize several functions such as low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP). The proposed configuration employs three input voltages and generates a single output voltage. The filter characteristics, i.e., pole frequency (ωp) and quality factor (Q) are electronically tunable through the bias current of the VDVTA. The filter performance is analysed through sensitivity analysis in presence of parasitics as well as process, voltage and temperature fluctuations. The proposed design is implemented in a 45-nm CMOS technology and simulated using Virtuoso Analog Design Environment of Cadence. [ABSTRACT FROM AUTHOR]

This paper presents a three-electrode potentiostat transducer circuit for electrochemical sensing system designed for biomolecular detection. Melatonin has been found to be used as a significant index of potential breast cancer risk. The proposed chip automatically measures the redox current which depends on the concentration of melatonin in the analyte solution. Moreover, a current-to-time converter is designed to convert the sensed current into the proportional digitized time signal for back-end signal processing. Cyclic voltammetry and molecularly imprinted polymers were used in the experiments. The sensing electrodes were coated with a thin film imprinted with the target molecule. Fabricated in the TSMC CMOS 0.18 μm 1P6M technology, the proposed chip has a core chip size of 0.083 mm2 and a power consumption of 1.143 mW with a 1.8 V supply voltage. This chip can measure the sensed current from ±15 to ±1500 µA with a linearity of R2 = 0.999. In the cyclic voltammetry measurement, this chip has an error of less than 0.7%. The urine measurement results of the proposed chip were compared with that of enzyme-linked immune sorbent assay. Verified by melatonin concentration measurement, the proposed chip with high sensitivity demonstrates the feasibility of melatonin concentration detection, which contributes to the examination of breast cancer. [ABSTRACT FROM AUTHOR]

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (Cin) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of −188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm2, i.e. 0.315 mm2. [ABSTRACT FROM AUTHOR]

Although studies have investigated the effects of flicker noise on randomness, such effects demand further examination. Despite the random nature of flicker noise, a coloured distribution is observed in the power spectral density of flicker noise, indicating to a correlation in between adjacent samples. Studies have employed ring oscillators (ROs) that produce random numbers by sampling the digitised analogue signals of their outputs. This sampling procedure may change the spectral properties of flicker noise resulting from the folding effect of noise. Another topic of interest regarding sampled flicker noise is its random behaviour. To investigate the contribution of flicker noise, white noise, and their combination to randomness, we produce synthetic bit streams of these noise sources. From observations, we find that flicker noise contributes to the entropy of bit streams. Using the generated synthetic bit streams, we also explore the entropy dependence of a bit stream on the sampling period and analyse and compare the entropy levels of the outputs of ROs operating in strong and weak inversion. Results of the comparison demonstrate that only one RO operating in weak inversion may be sufficient to attain the required entropy level for qualifying the generated bit stream as random. The results of the analysis are also confirmed by measurements. In addition, the paper proposes an efficient design of a RO-based random number generator. [ABSTRACT FROM AUTHOR]

In this paper, we present a multi-objective optimisation technique for transistor sizing in the variation-prone nanometric complementary metal-oxide semiconductor (CMOS) logic cells. To demonstrate the effectiveness of the technique, we have used the common figures-of-merit, such as power, energy, and static noise margin. By using examples of different logic cells, we have demonstrated how competing design goals can be tackled effectively. We show that concurrent improvements in multiple figures-of-merit are possible using the proposed method. [ABSTRACT FROM PUBLISHER]

This paper presents a single-stage input-powered bridge rectifier with boost switch for wireless-powered devices such as biomedical implants and wireless sensor nodes. Realised using CMOS process technology, it employs a duty cycle switch control to achieve high output voltage using boost technique, leading to a high output power conversion. It has only six external connections with the boost inductance. The input frequency of the bridge rectifier is set at 50 Hz, while the switching frequency is 100 kHz. The proposed circuit is fabricated on a single 0.18-micron CMOS die with a space area of 0.024 mm2. The simulated and measured results show good agreement. [ABSTRACT FROM AUTHOR]

A current-mode digital-to-analog converter designed by combining the weighted-current-steering approach and the R-βR ladder approach is proposed in this paper. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-βR ladder approach that is modified form the R-2R approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18 µm 1P6M CMOS process. Simulation results show that this design achieves a 16 b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3 V supply voltage and 200 MHz operating frequency, the power consumption is 232 mW. [ABSTRACT FROM AUTHOR]

This paper proposes an 8 × 8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8 × 8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35 μm standard CMOS process. [ABSTRACT FROM AUTHOR]

This paper describes an 11-Gb/s CMOS demultiplexer with redundant multi-valued logic. The proposed circuit receives serial binary data which is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the redundant multi-valued logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. The circuit is designed with a 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The demultiplexer is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at a higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency. [ABSTRACT FROM AUTHOR]

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13 µm CMOS technology with a power supply of 1.2 V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation. [ABSTRACT FROM AUTHOR]

A novel complementary metal-oxide semiconductor (CMOS) low noise amplifier (LNA) was designed in this paper for wireless local area network (WLAN) applications in the 5.8 GHz ISM band. The LNA presents low voltage and low power dissipation design integrated in TSMC 0.18 µm standard CMOS technology and achieves a gain of 15.2 dB, a noise figure of 2.5 dB and an IIP3 of -6.5 dBm with input return loss -38.5 dB, output return loss of -46.1 dB while dissipating just 4.96 mW from a 1V supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, the design and realization of an analogue CMOS prototype vision chip for grey level image segmentation for two regions is presented with Fuzzy- Kohonen Network processing as an alternative to neurontorphic and cellular neural networks approaches for vision chips. This alternative is due to the compensation that fuzziness gives in order lo utilize simple analogue circuits with small layout areas instead of robust analogue circuits with bigger layout areas required. This helps to relieve the signal to noise ratio when crisp computations are present. The vision chip is based on the elaboration of an array of basic cells that work simultaneously. Every basic cell has embedded one vertical phototransistor and one network implemented under weak inversion techniques. The chip processes one image in 35 us with consumption of 733 uW per cell, signal to noise ratio of 43dB and dynamic range of 49dB. [ABSTRACT FROM AUTHOR]

A bulk-isolated curvature-compensated bandgap voltage reference (BGR) compatible with triple-well CMOS technologies is presented in this paper. Verification results of the proposed BGR implemented in a 0.35-µm 3.3-V triple-well CMOS technology demonstrate that the BGR achieves a reference voltage of 220.4 mV with an average temperature coefficient (TC) of 3.7 ppm/°C in the −40 to 130°C range with 8-bit trimming. The measured current consumption and power supply rejection of the circuit are 33.15 µA and −69.51 dB at 100 Hz, respectively (VDD = 3.3 V). The circuit is capable of operating with supply voltages down to 2 V and its line regulation is 0.16%/V over a voltage range from 2 to 3.6 V. The root mean square output noise voltage in the 0.1–10 Hz frequency range is 2.54 µV. Moreover, measurement results show that the substrate noise sensitivity at the BGR output improved more than 30 dB for frequencies up to 50 kHz, thanks to the employed block bulk isolation strategy, although the effective improvement is expected to be more than 75 dB without the coupling from the electrostatic discharge diode in the I/O pad. [ABSTRACT FROM AUTHOR]

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m2. [ABSTRACT FROM PUBLISHER]

A CMOS integrable circuit technique for the realization of both a sinusoidal frequency doubler and a full-wave rectifier is described in this paper. The realization method makes use of the characteristic of a simple CMOS class AB amplifier configuration. Simulation and experimental results demonstrating the circuit performance are also included. [ABSTRACT FROM AUTHOR]

This paper provides an analysis of the static and dynamic working of the basic building blocks for hybrid-mode CMOS circuits. As a result of the analysis, simplified expressions are obtained which are adequate for the electrical design, layout and performances evaluation of these integrated circuits. The paper also includes SPICE simulation results proving the validity of the models developed. [ABSTRACT FROM AUTHOR]

A new high-speed high-resolution CMOS comparator is reported in this paper. A new offset-voltage-cancellation technique is used to reduce the effect of clock feed-through or charge pumping. The effective input voltage is doubled by the use of a cross-multiplexed technique. SPICE simulations using a modified MOS3 model (Wong 1986) show that the comparator reported here is capable of resolving 40 μV in less than 2·5 μs and 100 μV in 1 μs. [ABSTRACT FROM AUTHOR]

This paper presents new function generators (non-linear converters) with improved performance. It is shown that non-linear converters such as multiplier-dividers, generalized integrators and universal piecewise-linear function generators can be realized by using time-division principles and switched-capacitor (SC) techniques. In order to design such converters unified stray-insensitive, offset-compensated CMOS SC subcircuits (macrocells) are used as basic building blocks. The proposed structures have been constructed, experimentally tested and applied to solve some problems with accurate results. [ABSTRACT FROM AUTHOR]

In this paper, a new lumped element latchup model which includes two extra bipolar transistors is proposed. The divergence between the results of the conventional and the proposed model is explained in terms of the circuit parameters. The output behaviour of CMOS latchup and the output latchup mode are discussed in connection with the proposed model and the predictions of the model are compared to the results of the conventional model using SPICE. [ABSTRACT FROM AUTHOR]

In this paper we utilize an algorithm (Chiang and Vranesic 1983) to test for the classical stuck-at-fault nodes in CMOS transistor level circuits. The original algorithm may incorrectly produce input test patterns. In this paper we suggest a modification to rectify the algorithm. We demonstrate the testing of stuck-at-faults using our modified algorithm in addition to testing of transistors open/short faults. A complete test set for a fault is defined as the set of all input patterns that can detect that fault. Our modified algorithm differs from the original algorithm in that it produces the complete test set for each possible fault. The original algorithm stops searching once it reaches a test set capable of testing all faults. The set which is produced is not guaranteed to be neither complete nor minimal. Finally the paper introduces some programming techniques used in implementing the algorithm. [ABSTRACT FROM AUTHOR]

This paper presents a synthesis method for three-valued CMOS logic circuits that is essentially based on the use of the T-gate. P and N modules, subsets of the ternary T-gate, are defined and used as building blocks together with four types of ternary inverters to realize three-valued logic systems. First unary functions are realized, then multi-variable circuits are synthesized. Minimization techniques of ternary logic circuits based on the proposed synthesis method are also discussed. [ABSTRACT FROM AUTHOR]

In this paper, the new CMOS circuits for logical-sum and logical-product are proposed. In the case of two inputs, each of such proposed circuits can be composed of a pair of PMOS and NMOS transistors with threshold voltages close to zero volts. The model-parameters of such transistors are presented. It is shown that they are also very well suited for the traditional two-valued logic circuits. Various inverter-circuits to be used in the multiple-valued logic circuits, as well as the above proposed circuits, are also presented. The design method for four-valued combinational circuits using these circuits, together with the examples of their applications, are introduced. The simulation results of such combinational circuits using SPICE-2 are shown with satisfactory characteristics. [ABSTRACT FROM AUTHOR]

As the complementary metal oxide semiconductor feature size shrinks further, single event multiple transients (SEMTs) become more serious. However, SEMTs have not yet been appropriately modelled through traditional soft error rate (SER) estimation methods. Therefore, this paper presents a mixed-level framework to estimate SER induced by SEMTs. The precision of the proposed framework is verified through HSPICE simulation. The results show that multiple pulses and convergence of SEMTs significantly affect SER estimation. [ABSTRACT FROM PUBLISHER]

A low-power hybrid digital pulse width modulator (DPWM) is proposed in the paper. Owing to the piecewise calibration scheme, the delay time of delay line is locked to target frequency. The delay line consists of two piecewise lines with different control codes. The delay time of each cell in one sub-delay-line is longer than the last significant bit (LSB) of DPWM, while the delay time of each cell in the other sub-delay-line is shorter than LSB. Optimum linearity is realised with minimum standard cells. Simulation results show that the differential nonlinearity and integral nonlinearity are improved from 5.1 to 0.4 and from 5 to 1.3, respectively. The DPWM is fully synthesised and fabricated in a 90-nm CMOS process. The proposed DPWM occupies a silicon area of 0.01 mm2, with 31.5 μw core power consumption. Experimental results are shown to demonstrate the 2-MHz, 10-bit resolution implementation. Pulse width histogram is firstly introduced to characterise the linearity of the DPWM. [ABSTRACT FROM PUBLISHER]

This paper presents an on-chip process, voltage and temperature (PVT) compensation technique for a 1-MHz monolithic clock oscillator in a CMOS process. The oscillator is based on carrier mobility and frequency-to-voltage converter (FVC), which is based on charge pump circuit. An adaptive charge current maintains a constant frequency without trimming. Furthermore, a reference voltage with a second-order temperature coefficient further compensates the variation of frequency with temperature. It improves the accuracy of existing carrier-mobility-based oscillator, from 4.5% to 2.3%. The circuit was designed in a 130 nm CMOS 3.3 V device process. The results show that the output frequency is within2.3% variation in the worst case. The variations of frequency with process, temperature (−40 to 125°C) and power supply are within1.8%,0.8% and0.2%/V, respectively. It achieves a CMOS monolithic clock oscillator insensitive to PVT. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a 2.5/3.5-GHz dual-band low-power and low-noise CMOS amplifier (LNA), which uses the capacitor cross-coupling technique and current-reuse method with four switches. The proposed LNA uses a single RF block and a broadband input stage, which is a key aspect for the easy reconfiguration of a dual-band LNA. Switching at the inter-stage and output allows for the selection of a different standard. The dual-band LNA attenuates the undesired interference of a broadband gain response circuit, which allows the linearity of the amplifier to be improved. The capacitor cross-coupled gm-boosting method improves the NF and reduces the current consumption. The proposed LNA employs a current-reused structure to decrease the total power consumption. The inter-stage and output switched resonators switch the LNA between the 2.5-GHz and 3.5-GHz bands. The proposed dual-band LNA optimises power consumption by the securing gain, noise figure and linearity. The simulated performance reveals gains of 16.7 dB and 19.6 dB, and noise figures of 3.04 dB and 2.63 dB at the two frequency bands, respectively. The linearity parameters of IIP3 are −5.7 dBm at 2.5 GHz and −9.7 dBm at 3.5 GHz. The proposed dual-band LNA consumes 5.6 mW from a 1.8 V power supply. [ABSTRACT FROM PUBLISHER]

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm2, which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz. [ABSTRACT FROM AUTHOR]

This investigation demonstrates a 10-bit SAR-ADC with low power dissipation per conversion step at 50 MS/s sampling rate. The proposed ADC is featured with the split-capacitance array by using unity-gain amplifiers and designed for fibre optic gyroscope (FOG) systems. The buffers based on the unity-gain amplifiers replace the bridge capacitors of the split-capacitance array in conventional SAR ADCs to resist process variation and enhance linearity of the capacitor-array. Aside from those, improvements in time response, that is, settling time, and capacitor size have also been proved. The design was implemented using a typical 40-nm CMOS process. The INL (integral non-linearity) and the DNL (differential non-linearity) were found to be 0.56 LSB and 0.51 LSB, respectively. The SNDR and SFDR are 51.23 dB and 61.46 dB, respectively, at an input of 12.5 MHz showing ENOB to be 9.79 bits at a sampling rate of 50 MS/s. [ABSTRACT FROM AUTHOR]