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Summary: The central nervous system receives a vast amount of sensory inputs, and it should be able to discriminate and recognize different kinds of multisensory information. Winner‐take‐all (WTA) consists of a simple recurrent neural network carrying out discrimination of input signals through competition. This paper presents a real‐time scalable digital hardware implementation of the spiking WTA network. The need for concurrent computing, real‐time performance, proper accuracy, and the reconfigurable device has led to the field‐programmable gate array (FPGA) as the target hardware platform. A set of techniques is employed to lessen memory and resource usage. The proposed architecture consists of multiprocessing elements, which share hardware resources between a specific number of neurons. We introduce a novel connectivity array for neurons (dedicated to the WTA network) to cut down memory usage. Also, a multiplier‐less method in the neuron model and a novel tree adder in the synapse processing unit are designed to improve computational efficiency. The proposed network simulates 4,500 neurons in real time on a Xilinx Artix‐7 FPGA, while a scalable architecture facilitates the implementation of up to 20,000 neurons on this device. The pipeline structure can guarantee real‐time performance for large‐scale networks. Based on simulation and physical synthesis results, the presented network mimics biological WTA dynamics and consumes efficient hardware resources. [ABSTRACT FROM AUTHOR]