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Summary: In this paper, for the first time, a new method with closed‐form analytical equations is presented to calculate the oscillation amplitude of fourth‐order oscillators, such as quadrature oscillators. This method is actually based on the general form of the differential equations describing the structure of the fourth‐order oscillators and finding a solution for the nonlinear differential equations governing this type of oscillator. The introduced method is a general method that is valid for all fourth‐order oscillators and is also independent of the oscillation frequency. Using the proposed method, complex and time‐consuming simulation tools will no longer be needed to calculate the oscillation amplitude in a steady state. Moreover, the presented closed‐form equations help the designers to understand the design compromises and design the oscillator for their specific and desired conditions. In addition, to evaluate the correctness of the presented equations, a comprehensive analysis of the oscillation amplitude of the quadrature oscillator in the steady state is performed, and a closed‐form equation is presented for the oscillation amplitude of the oscillator in the steady state, which is proposed for the first time in this paper. A comparison between the simulation results and theoretical computations confirms the validity of the proposed method. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes a self‐powered SSHI piezoelectric energy extraction circuit combined with Modified FOCV‐MPPT technology, which analyzes the electrical characteristics of S‐SSHI operation. The paper demonstrates that the determination of the optimal operating state of S‐SSHI can be determined independently of the open‐circuit voltage. Based on the key parameters obtained from the theoretical analysis, the FOCV‐MPPT strategy is modified, and the corresponding functional circuit is designed. This strategy serves as an intermediate stage between S‐SSHI and the load, addressing the dependence of S‐SSHI output power on the load while avoiding the power supply interruption issue of the traditional FOCV‐MPPT strategy. In addition, the higher output power provided by S‐SSHI improves the utilization of MPPT technology. The correctness of the investigations is verified through the simulation and experiments. By using self‐powered S‐SSHI, the proposed circuit increases the output power of PEH by a factor of 2.46. In the open‐circuit voltage range of 2–7 V, the average maximum power tracking efficiency achieved 90.1%. The maximum tracking efficiency can reach 98%. [ABSTRACT FROM AUTHOR]

Summary: The large integration of distributed generation (DG) and electric vehicles (EVs) facilitates daily life and reduces carbon emissions. However, it brings problems such as increased uncertainty and power electronic permeability to the distribution network. In this context, it is important to solve the line loss optimization problem as closely as possible to the real situation. Therefore, this paper solves the line loss optimization problem based on a probabilistic model of three‐phase unbalanced modern power electrical distribution network. Firstly, the paper proposes a frequency domain model of the distribution network and the optimization problem model. Then, to deal with the uncertainty of the system, the point estimation method (PEM) and Monte Carlo Simulation (MCS) are used. Finally, this paper proposes two optimization schemes considering the power quality when single and multiple DGs are integrated. The simulation results demonstrate that the PEM using the Gram–Charlier series expansion of the fourth‐order statistical moments to estimate the probability density function (PDF) is significantly less time consuming than the traditional MCS method while maintaining accuracy. The comparative analysis reveals that under the optimization scheme with single DG integration, the expected value of system line loss and expected line loss rate are reduced from 283.95 kW to 218.96 kW (22.89% reduction) and from 13.44% to 10.68%, respectively. Under the dual DG integrated optimization scheme, the expected value of line losses and expected line loss rate are reduced from 283.95 kW to 208.88 kW (26.4% reduction) and from 13.44% to 10.25%, respectively. However, after taking the uncertainty into account, the operational reliability of the system has been enhanced under different scenarios. In addition, it is found that the optimization approach incorporating multiple DG units can effectively mitigate the system line loss under diverse operational scenarios while enhancing the system's DG integration capability. [ABSTRACT FROM AUTHOR]

When the resonant converters are connected in parallel, the output current is unbalanced without additional current‐sharing measures due to differences in resonant component. In the input‐parallel output‐parallel resonant converter system, the output voltage accuracy of the converter under the traditional droop control is analyzed when the load changes. In this paper, an adaptive droop control is proposed, in which the droop coefficient is adaptively adjusted as the load changes. The control method proposed in this paper realizes the current sharing between the converters and solves the shortcomings of the output voltage changing under different loads in the conventional droop control. Taking two parallel LLC converters as an example, the control block diagram of the parallel control method for adaptive adjustment of the droop coefficient proposed in this paper is given, and the stability of the control loop is analyzed. Finally, two parallel prototypes of LLC converters with input 200 V/output 24 V input are built by digital control, and the experiment shows that the proposed control method improves the shortcomings of excessive output voltage droop caused by traditional droop control during dynamic load switching, which verifies the effectiveness of the method. [ABSTRACT FROM AUTHOR]

Summary: Five‐level active neutral‐point‐clamped (5L‐ANPC) converters have great practical potential in the field of medium and high voltage variable frequency speed regulation. However, the dynamic and static voltage imbalance of the series IGBTs may cause permanent damage to the device, which limits its popularization and application. In this paper, an improved self‐balancing voltage 5L‐ANPC topology (ISBV‐5L‐ANPC) is proposed to address such voltage balancing problem as series switches and high voltage leaps, which realizes dynamic and static voltage equalization by connecting the self‐balancing module consisting of an auxiliary capacitor to the bridge arm, so that it clamps the series switches. In this paper, the operation principle of ISBV‐5L‐ANPC is given in detail, and the control strategy of ISBV‐5L‐ANPC is proposed, and the key parameters in the topology are analyzed and designed. Finally, an ISBV‐5L‐ANPC prototype was built, and the effectiveness of the proposed topology and the feasibility of the control strategy are verified through the experimental results. [ABSTRACT FROM AUTHOR]

In this paper, the omnidirectional receiver (Rx) of wireless power transfer (WPT) system is proposed, making any transmitter (Tx) into omnidirectional Tx. The omnidirectional Rx is composed of the quadrature double‐D (DD) coils and circular coil in series (C2DD). The C2DD Rx can utilize the toroidal magnetic field (TMF) and the linear magnetic field (LMF). The paper presents the circuit diagram model of WPT system. Based on the analysis of circuit model, the smooth mutual inductance of system is responsible for stable transmission performance during C2DD Rx movement. The result of numerical calculation and magnetic field simulation verifies the omnidirectional capability of the C2DD Rx with circular Tx as an example. Experiment shows that the C2DD Rx receives power in any direction. The C2DD Rx can receive maximum transmission power of 7.1 W with maximum transmission efficiency of 59%. [ABSTRACT FROM AUTHOR]

Summary This paper proposes a single‐phase dual‐input step‐up switched‐capacitor multilevel inverter that employs three capacitors, 15 switches, and two diodes to provide 13 voltage levels and triple‐voltage boosting factor in its symmetric form and 37 levels with voltage boosting factor of 3.6 in its asymmetric version. This high boosting factor is accomplished without utilizing any transformer. For each output voltage level, there exists flow paths for both the positive and negative load current directions, which makes the proposed inverter capable of supplying any load type with variety of power factors (zero to unity). The voltage balancing of the capacitors takes place naturally, which tackles the need to auxiliary charge‐balancing circuits or control mechanisms. The proposed inverter can generate negative levels without the end‐side H‐bridge. Moreover, the voltage stress on the semiconductor devices is less than the peak output voltage. The increased number of levels and sinusoidal‐like waveform of the output voltage waveform enhances the quality and lowers the harmonic content of the load voltage and current waveforms, even for resistive loads. As the result, the load‐side filter can be downsized or removed. This paper employs the fundamental frequency method (FFM) as the switching technique, which is simple to implement and also operates the switches at low frequencies, leading to lower switching losses. The ascendancy of proposed inverter over similar counterparts has been investigated through comprehensive comparative analysis. Moreover, the correct performance of the proposed inverter at different modulation indices, and load types as well as during dynamic load changes has been verified by simulation and experimental analysis. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers (PAs) designed for 35–42 GHz millimeter‐wave applications, utilizing a 130 nm CMOS process. The proposed RF PAs are well suited for wide frequency‐band millimeter‐wave and 5G radio transmitters. A comprehensive study of limiting factors in amplifier efficiency is presented in this paper. The study encompasses an analysis of all the factors that restrict the efficiency of the switched power amplifier. The first proposed power amplifier is based on the Class E/F2 architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network. Conversely, the second suggested power amplifier is constructed using the inverse Class‐‐F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed Class E/F2 and inverse Class‐‐F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency. The suggested power amplifiers comprise a driver Class‐‐AB stage and a power stage constructed based on either the Class E/F2 architecture or inverse Class‐‐F topology, utilizing harmonic termination networks at the output load. Two new designs of high‐Q factor on‐chip finger capacitors have been implemented to improve efficiency and radio frequency performance. Achieving input matching and inter‐stage matching is facilitated by employing two novel on‐chip transformers designed for maximum power transfer. Additionally, an inter‐stage matching inductor is utilized in a cascode configuration to enhance the overall RF performance. The on‐chip transformers, inductors, and finger capacitors are designed using the HFSS software program. S‐parameter files (SNP files) of the designed on‐chip components are extracted and inserted into the simulation tool to ensure accurate results. The proposed Class E/F2 power amplifier achieves a constant power of 14.9 dBm, an extreme power added efficiency (PAE) of 11.7%, and a maximum gain of 13.74 dB. In contrast, the suggested inverse Class‐‐F power amplifier attains a constant power of 15.4 dBm, a peak PAE of 12.6%, and a maximum gain of 14.8 dB. The DC power consumption is 73 and 66 mW for the proposed Class E/F2 and inverse Class‐‐F PAs, respectively, while their active sizes are 0.14 and 0.2 mm2. [ABSTRACT FROM AUTHOR]

Summary Brushless DC motors (BLDCs) are highly efficient and have the least maintenance requirement due to which they have replaced many conventional AC motors in various applications like electric vehicles, fans, water pumps, and home appliances. However, like all conventional motors, performance degradation of the BLDC motors can occur due to faults like Hall sensors failure, commutation switch failure, and stator‐winding failure. Among all these failures, this paper focuses on Hall sensor failures and the execution of fault tolerant control. Hall sensors produce an output after every 60° of rotation of the rotor, generating six sequences in one electrical cycle. In this study, each sequence is defined as a sector, which corresponds to the rotor position. Based only on this sector information in each electrical cycle, this paper proposes an uncomplicated detection strategy for Hall sensor fault, which is independent of motor loading and high‐performance processing unit. Along with the diagnosis, an improved faulty signal reconstruction is implemented, which bypasses the fault and continues a smooth performance of the motor. The proposed detection and reconstruction strategies have been simulated in MATLAB Simulink 2020, and the experimental analysis has been conducted to validate the proposed strategies. [ABSTRACT FROM AUTHOR]

Summary This paper proposes an integrated modular equalization circuit for energy storage systems. This integration is achieved by reusing the half‐bridge circuit into the cell‐level equalization circuit and the module‐level equalization circuit, thereby simplifying the system. The proposed equalization circuit has a good equalization effect and balancing speed. In addition, all high‐frequency switches in the equalization circuit can achieve zero voltage switching (ZVS), and the equalization circuit has high efficiency. This paper provides a detailed analysis of the equalization circuit. Mathematical models for cell‐level and module‐level equalization circuits have been derived for optimal design and control of the equalization circuit. The experimental results have good consistency with the analytical results. [ABSTRACT FROM AUTHOR]

Summary This paper introduces an equivalent model including the parasitic parameters analysis of silicon carbide (SiC) MOSFETs in order to enhance their performance for high‐power density applications. The model is used to establish a mechanism that evaluates the effect of drive parameters on switching losses and electrical stress of power devices, providing a theoretical basis for optimizing the design of drive parameters. The paper finds the Pareto solution of the multi‐objective optimization model through iterative calculation of design variables, using this mechanism. The methodology is validated through experimental results from an SiC power prototype, showing an efficiency of 98.9% and safe electrical stress levels under 1500 V/100 kW operating conditions. [ABSTRACT FROM AUTHOR]

Summary In this paper, a new stacked bidirectional non‐isolated DC‐DC converter for uninterruptible power supply applications is presented. It is a stacked adaptation of the classical bidirectional boost/buck converter and presents improvements such as low number of components; low voltage and current stress on components; high efficiency; and simplicity of operation. In addition, in this paper, the modeling and control of the proposed converter are done, and a comparative evaluation among proposed converter with similar topologies is evaluated. A prototype of 1 kW, 144 to 400 V, is developed in laboratory to validate the theoretical evaluations of proposed converter. Besides that, the proposed converter is also evaluated under different dynamic condition, which illustrates the effectiveness of the converter. Finally, the maximum efficiency obtained is 96.38% in step‐up mode and 95.7% in step‐down mode. [ABSTRACT FROM AUTHOR]

Summary A DC to AC converter is developed in this paper. This proposes a single‐phase five‐level inverter is developed in such a way that one DC source is used. The structure of the inverter is modular and the capacitor has self‐voltage balancing capability, which eliminates the need for sensors or an additional control loop. This paper presents the schematic diagram of the proposed topology, principle of operation, and the concepts of sinusoidal pulse width modulation (SPWM) for single‐phase and space vector pulse width modulation (SVPWM) for three‐phase. To further prove the advantage, power loss, and parameter computations are calculated mathematically. Low‐voltage stress is achieved in the proposed topology because the blocking voltages of all the switches are constrained to the input voltage. A comparison table is presented between SPWM and SVPWM schemes in three‐phase inverter. The proposed asymmetrical five‐level configuration setup is constructed, and experiments are performed inside the laboratory. The controller of the converter has been implemented in the field‐programmable gate array (FPGA) platform. In order to confirm the viability of the suggested topology, experimental results are provided for single‐phase arrangement. By using the FPGA platform, real‐time implementation is done for a three‐phase inverter topology. [ABSTRACT FROM AUTHOR]

This paper proposes a transformerless common ground based single phase single‐stage switched boost inverter for solar photovoltaic (PV) applications. In the proposed inverter, the input DC source and output AC load share a common ground. As a result, the high‐frequency common mode voltage across the parasitic capacitance is eliminated, resulting in negligible leakage current (iLK) and the associated power loss, and harmonics in the inverter. Moreover, the higher voltage gain of the inverter facilitates the inverter to operate with high modulation index and lower shoot through (ST) duty ratio. Hence, the DC link voltage requirement across the inverter leg is reduced. Consequently, the voltage stress across the switches is minimized. Here, a modified PWM control technique is adopted, where the dual active states of the proposed inverter reduce the inductor current ripple and make it suitable for solar PV applications. The voltage boosting capability of the proposed inverter is extendable with the help of an additional number of intermediate impedance sub‐networks. The detailed steady‐state analysis of the proposed inverter is verified with the help of MATLAB simulation. To verify the simulation results, a 200 W, 120 V, and 50 Hz experimental prototype is developed. The prototype is tested for unity and lagging power factor load conditions with a wide range of input DC voltages, and all the major results are included in the paper. The power and thermal loss analysis is carried out using PLECS software, and the results show that the inverter has a maximum efficiency of 97.48%. From the experimental results, it can be inferred that the proposed inverter has a higher modulation index, lesser inductor current ripple, and zero leakage current as compared to the contemporary inverters. [ABSTRACT FROM AUTHOR]

Summary: The sensorless speed control of permanent magnet synchronous motor (PMSM) is gaining popularity in hybrid electric vehicle (HEV) applications leading to its enhanced safety, reliability, and cost savings. Speed control using vector control for PMSM‐fed HEV requires the speed encoder. When the speed sensor information fails, the inverter must ensure power delivery to the PMSM continuously by estimating the speed; this mode of operation is referred as limp‐home mode in HEV. In this paper, a speed sensorless scheme has been proposed for PMSM‐based HEV during limp‐home mode operation. This paper presents a model reference adaptive system (MRAS) speed estimator based on an adaptive neural network controller (NNC) for speed estimation of PMSM. In the HEV application, in case of speed/position encoder failure, the speed of the PMSM can be estimated by stator flux using stator current.The proposed method employs stator currents in the reference model to eliminate the DC drift problem. Furthermore, the NNC is employed in the adaptation mechanism to improve the Federal Test Procedure (FTP75) driving cycle performance. The performance of the proposed control scheme has been validated with dSPACE 1104 R & D rapid development controller using vector control for the PMSM during variable speed and torque, including the zero‐speed applications [ABSTRACT FROM AUTHOR]

Summary: This paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 μW. The transceiver has an area of 1.016 × 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit. [ABSTRACT FROM AUTHOR]

An improved carrier‐based pulse‐width‐modulation (CBPWM) technique for a three‐level (3L) F‐type neutral point‐clamped (FNPC) inverter is presented in this paper. By using the proposed modulation scheme, the DC‐link capacitor voltage at the neutral point is balanced. For manufacturers, reliability is one of the major concerns for all power electronics devices and parts. This paper proposes an extensive reliability analysis of the 3L‐FNPC inverter. Considering the mean time to failure (MTTF) of each device, the reliability of the 3L‐FNPC inverter is analyzed in this present work by using two different methods, which are the approximate method and the exact method. To compute the failure rate of the equipment, only the number of components is considered in the approximate method. Alternatively, exact methods are utilized to evaluate the reliability of a system by knowing the different stress levels and various operating environments of a specific system. Because of the strong correlation between device failure and temperature stress factors, power loss analysis is used in the exact method. The MATLAB Simulink environment is used to determine the power loss of the switching devices. A solar off‐grid photovoltaic (PV) system is considered for reliability testing. Experimental mission profile data are used to estimate the lifetime of the 3L‐FNPC inverter by applying the rainflow counting algorithm, the Coffin‐Manson model, and Miner's rule. The competitiveness, effectiveness, and reliability of the 3L‐FNPC inverter with the proposed modulation technique are validated using a hardware prototype. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes leaky least mean fourth (LLMF) algorithm for the control of five‐level series connected H‐bridge multilevel inverter (5L SCHB‐MLI). The SCHB multilevel inverter is a popular configuration due to its wide application for high‐power and medium‐voltage applications. The complete system comprising the grid, load, and compensator is modeled in MATLAB/SIMULINK. Prototype hardware is also developed in the laboratory for experimental validation. The 5L SCHB inverter is connected in a single‐phase power distribution system and controlled as a compensator. The voltage across both DC links of the H‐bridges is regulated to almost equal value by the proposed control algorithm. The closed loop system is designed to mitigate total harmonic distortion (THD) in the source current and improve the power quality of the proposed system. The system is analyzed under the steady state and dynamic state, and the results are also verified on the hardware prototype developed in the laboratory. The proposed algorithm is also compared with conventional least means square (LMS) algorithm and notch filter algorithm on several parameters. The paper discusses a detailed simulation and hardware analysis on the control of five‐level MLI topology. [ABSTRACT FROM AUTHOR]

Summary Commutation torque ripple occurs when brushless DC (BLDC) motor runs in the high‐speed range, which degrades operation performance. To overcome the problem, this paper presents a commutation torque ripple suppression method based on the minimum phase shift angle (MPSA) of hall signals. In the paper, the effect of the phase shift angle (PSA) of hall signals on phase current is analyzed, and the MPSA is deduced on the basis of the unit duty cycle of the incoming and non‐commutation phase. With the proposed method, two‐phase conduction mode is used in the full speed range, commutation period and non‐commutation period, which avoids switching modulation mode and enhances system reliability. The proposed method is implemented through shifting hall signals by the MPSA, and it is simple and feasible without the requirement to redesign a controller. Moreover, no additional power devices and precise sensors are required, which reduces design cost and volume size. The proposed method is experimentally compared with different methods under steady operation condition, and the results show superior performance on suppressing commutation torque ripple. The loading experiment demonstrates that the proposed method exhibits good dynamic response. The frequency spectrum of the electromagnetic torque is analyzed, and it is verified that the 6nf harmonics are diminished with the proposed method. [ABSTRACT FROM AUTHOR]

Summary In wireless charging systems for electric vehicles, fluctuations in coil mutual inductance can affect both system output power and efficiency. This paper introduces a coil mutual inductance model that accounts for metal shielding material. The formula for coil mutual inductance is derived using Maxwell's equations and boundary conditions. Additionally, the paper presents a tactic for adapting the mutual inductance with the aid of an intelligent optimization algorithm, which is utilized for steadying the mutual inductance of the transmission coil. Lastly, a model of the transmission coil is developed to authenticate the practicality of the mutual inductance equation and the adaptation scheme. Measurement and calculation results indicate that the difference between the calculated value of the mutual inductance formula and the actual mutual inductance value of the coil, following deflection and offset, is below 5%. Moreover, the algorithm, along with the employed adaptation strategy, consistently demonstrates effectiveness in maintaining the mutual inductance value within a predefined range. The temporal efficiency of the algorithm, as measured by the time taken to determine this coordinate position, is consistently under 1 s. This ensures that the algorithm exhibits a rapid response time, a crucial attribute in ensuring its practical utility. [ABSTRACT FROM AUTHOR]

Summary This paper targets to minimize the peak common mode voltage (CMV) in ultra sparse matrix converters (USMC) by applying new zero vectors for the space vector modulation technique (SVM). Conventional zero vectors in the SVM raise the peak CMV by 42.23%. An increased magnitude of CMV is associated with the occurrence of leakage current, hence resulting in insulation degradation. So, the reduction of peak CMV is necessary for USMC. The proposed method offers suitable switching arrangements using auxiliary shoot through (AST) switches to minimize the peak‐to‐peak CMV. This proposed method holds the advantages of the conventional method, like a wide range of modulation index and zero current switching at the rectifier side, and also reduces the CMV problem. This paper also provides a comparative analysis of the existing reported methods and the proposed method. The effectiveness of the proposed method is validated through both simulation and experimental results. [ABSTRACT FROM AUTHOR]

Summary: This paper presents Doherty power amplifier (DPA) based on gallium nitride (GaN) technology, incorporating a parallel grounded network with series RC elements in front of the carrier and peaking amplifiers to enhance circuit stability. In comparison to the traditional series network with parallel RC structure, this configuration effectively reduces the sensitivity of the stability factor K to the capacitance value within the stability network. Consequently, it mitigates the impact on various performance indicators such as gain and drain efficiency, addressing the issue of measurement performance deviation caused by inaccurate capacitance models in the simulation files, which is particularly crucial for DPA. As a result, the circuit exhibits improved consistency in design and processing. With full band stability, the DPA achieves a saturation output power of approximately 29.8 dBm at 28 GHz, a saturation efficiency of 38.2%, and a 6‐dB back‐off efficiency of 29.6%. [ABSTRACT FROM AUTHOR]

Summary: In many practical applications such as motor drives, the inverter is required to produce a variable output voltage within a wide range (e.g., 0.1 to 1 pu). In such cases, when the inverter operates in low modulation index (low output voltage), the harmonic distortion of the output voltage increases due to considerable reduction in the magnitude of the fundamental component. Also, the ratio of the switching losses to the output power will be high in the low modulation index. In this paper, a simple solution is proposed to overcome the problems. The principle of the proposed solution is to adjust the DC‐link voltage so that the modulation index of the inverter remains within a specific high range. Different practical ways of obtaining controlled DC‐link voltage are presented. Also, for operation of the DC‐DC converter used for DC‐link voltage control, three strategies are proposed. The proposed solution is simple, and it is very effective and feasible to implement. To the best of the authors' knowledge, the idea has not been presented in this form previously. In order to verify the proposed solution, the simulation and experimental results are presented and discussed. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes a new extendable multicell topology based on the conventional quasi‐Z‐source converter (QZSC). The proposed topology has a multicell scheme and employs an active switched capacitor/inductor (ASC/SL) network. Therefore, it is entitled extended multicell ASC/SL QZSC (EMc‐ASC/SL‐QZSC). The proposed topology is augmented by cascading a modular cell consisting of two capacitors, an inductor, and a diode. The EMc‐ASC/SL‐QZSC offers significant advantages over existing QZSC‐based configurations. It has a high boosting capability that results in a wider output voltage range while simultaneously reducing voltage stress on capacitors and switching devices, all without losing voltage gain. Furthermore, this topology effectively reduces input current ripple, which contributes to a smoother charging current profile for capacitors, reducing electromagnetic interference (EMI) and improving overall efficiency. The practicality and performance of the EMc‐ASC/SL‐QZSC topology are comprehensively assessed through extensive numerical simulations and experimental verification, utilizing a laboratory‐built prototype. [ABSTRACT FROM AUTHOR]

Summary: The application of modular multilevel converters (MMC) in medium voltage static synchronous compensators (STATCOMs) has been investigated in recent years. A huge challenge for MMC‐STATCOM is to compute the gain of the controllers. Therefore, the contribution of this paper is the proposal of a control tuning methodology for MMC‐STATCOM. For this purpose, the control and tuning strategies are presented. Since MMC‐STATCOM can employ different modulation strategies, two distinct modulation strategies are considered: nearest‐level control, with variable switching frequency; and phase‐shifted carrier pulse‐width modulation, with fixed switching frequency. Moreover, the proposal was validated through simulation and an experimental platform. The results indicate that the power response follows the reference, besides supplying the internal losses of the converter. The 10% ripple tolerance of the submodule voltages is respected in steady state for both modulation strategies. Moreover, the 5% total demand distortion (TDD) limit recommended by the Institute of Electrical and Electronics Engineers (IEEE) standard is attended. These results demonstrate the effectiveness of the controls employed. [ABSTRACT FROM AUTHOR]

Summary: The process and design variations during fabrication generate random mismatch‐induced nonlinearities in Current steering DACs (CS‐DACs), which are the main reason for performance degradation. Considering this, a mismatch error compensation method is highly desirable to boost both static and dynamic performances for the wide‐band CS‐DACs. To address this issue, an on‐chip self‐healing assisted swap‐enabled randomization technique (SASR) is proposed in this work for the Nyquist band CS‐DAC structures. This paper presents a robust hybrid CS‐DAC architecture to enhance both static and dynamic performances. The partial self‐healing method measures and recovers the mismatch current of the current cells. Further, to reduce the mismatch‐based nonlinear distortions, swap‐enabled randomization technique is adopted. This enhances the high‐frequency spurious‐free dynamic range (SFDR) values by mitigating inter and intra‐segment mismatch errors. A higher figure of merit (FoM) is obtained for 10‐bit CS‐DAC architecture utilizing the proposed SASR technique compared with state‐of‐the‐art DACs, which indicates the suitability for higher precision and high‐speed CS‐DAC structures. [ABSTRACT FROM AUTHOR]

In this paper, a low‐cost and high‐speed partial shading condition (PSC) detection scheme and global maximum power point tracking (GMPPT) technique are presented. The proposed technique detects the PSC using a low‐cost voltage sensor without setting any threshold parameter. The proposed GMPPT algorithm utilizes the 0.8 Voc model along with the load‐line observation to skip the unwanted interval of P– V curve. Moreover, in case of dynamic shading, a smart scanning mechanism is used along with the load‐line observation to reduce the voltage iterations which leads to an improvement in tracking speed. The proposed technique is implemented in a Matlab/Simulink environment and compared with the conventional 0.8 Voc method and accurate PSC detection method. The results indicate the following advantages of the proposed algorithm: (1) iteration free and accurate detection of PSC and uniform irradiance condition, (2) enhancement in average tracking time by 67.44% and 69.48%, and (3) improvement in average transient efficiency by 17.36% and 21.25% compared with 0.8 Voc method and accurate PSC detection method. Besides, the experimental results depict that the proposed method enhances the average tracking time by 68.6% and 72.69% and improves the average transient efficiency by 17.62% and 15.06% compared with 0.8 Voc method and accurate PSC detection method, respectively. [ABSTRACT FROM AUTHOR]

The boost‐flyback converter is a type of DC‐DC power converter that allows for efficient step‐up voltage conversion. Despite its potential for achieving high voltage gains, there is a lack of comprehensive analysis and practical implementation of reliable control methods for this converter. To date, only a few control techniques have been thoroughly examined and, more importantly, validated on hardware for this specific converter. In this paper, a comprehensive evaluation of two control techniques is presented, namely, zero average surface (ZAS) and hysteresis band (HB) control, for the boost‐flyback converter. Insights into the performance of these techniques and their applicability in real‐world scenarios are provided by experimental investigation. Experimental results have shown that the ZAS controller, while promising in theory, requires the inclusion of a secondary feed‐forward control loop to achieve accurate regulation of the output and effective disturbance rejection. This finding has highlighted the sensitivity of the ZAS control to measurement noise and the importance of careful consideration when implementing it in hardware. By providing a detailed comparison and insights into the performance of these control techniques, this study contributes to the advancement of control strategies for the boost‐flyback converter and guides future research in this field. [ABSTRACT FROM AUTHOR]

Location and navigation information has become an important part of our lives. GPS data is vital in many areas from transportation to economy, from energy to security. The alteration of this information can have deleterious downstream effects that cannot be reversed. Today, it is possible to attack GPS data with accessible hardware and open source software. In this paper, the signal obtained with the help of a transceiver that samples the high frequency RF signals down to the intermediate frequency was compared with the RMS value by windowing over PSD. Then this data was statistically analyzed with the NIST runs test. In order to realize GPS signal spoofing in a short time that after GPS receiver lock the spoofing signal, field programmable gates connected to the transceiver were used. The results obtained varied according to the dimensions of the windowing process, and it was understood that the window size was in a correlation with the detection of deception in a short time. The suggested method's key benefit is its simplicity, which makes it adaptable to various GNSS systems. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a vector‐sum phase shifter (VSPS) integrated with a wideband high‐gain low‐noise amplifier (LNA) for Ka‐band phased‐array receivers is presented. The digitally controlled VSPS based on the RF phase shifting architecture consists of a modified I/Q signal generator with additional inductor resonance and a programmable variable gain amplifier (VGA) based on Four 3 × 4 transistor arrays. Besides the reduced parasitic effect of the I/Q signal generator, an Equidistant Contraction Technology (ECT) is used in the VGA, to maintain higher phase shift accuracy of the VSPS. A multistage LNA with series inductor peaking is adopted to fulfill the flat wideband gain, where LC resonance networks are used as interstage matching to compensate for gain roll‐off at a higher frequency. Based on simulations in 65 nm CMOS technology, the presented LNA‐Phase shifter has achieved an average NF of 3.24–3.66 dB, and an average gain of 13.1–23.6 dB. Moreover, an RMS phase error of 1.1–12.6°, an RMS gain error of 4.2–5.6 dB, and an RMS magnitude error of 2.1–2.8 dB are maintained across 27–40 GHz, with a 360° phase shift coverage in steps of approximately 2.8125°. The chip consumes 16.83 mW from a 1.2 V supply voltage, and the occupied area is 0.65 mm2. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes a double‐node upset complete resilient (DNUCR) latch to meet the requirements of low orbit space applications for high robustness, cost‐effectiveness, and high performance. With the help of its interlocked loops with multiple feedbacks consisting of C‐elements (CE), input splitting CEs, 1P‐2N and 2P‐1N elements, and inverters, the proposed DNUCR latch preserves the original data even after the radiation incident. Error injection simulations in Synopsys HSPICE show that the proposed DNUCR latch recovers from all DNUs and can withstand large amount of injected charge. The simulation outcomes further show that the proposed DNUCR latch outperforms existing DNU‐resilient latches in terms of delay, power consumption, and power–delay–area product (PDAP), with an average of 48% reduction in delay, 22% savings in power, and 60% reduction in PDAP. The proposed DNUCR latch is also found to be the best among the existing radiation‐hardened latches in terms of charge‐to‐PDAP ratio. [ABSTRACT FROM AUTHOR]

Summary: In this paper, introduces a DC–DC converter design based on a modified hybrid switched inductor‐switched capacitor architecture, aimed at achieving ultra‐high voltage gain in renewable energy systems (RES). The proposed converter involves adding a modified boosting conversion mode (MBM) that interleaves with the main switch to double the voltage transfer gain. Additionally, a modified switched capacitor (MSC) technique, utilizing two diodes as interleaved components, is integrated into the main and auxiliary switches to verify low voltage stress across them. In addition, modified hybrid switched inductors with capacitors (MSIC) and diodes are employed to validate ultra‐high voltage gain. The main advantages of the proposed converter are its high efficiency, low voltage stress across diodes and MOSFETs, and the utilization of low values of inductors and capacitors at high switching frequencies. In addition, the voltage stress across the inductors of the (MSIC) is reduced as the duty cycle increases. Furthermore, the current stress on the main switch is reduced when the charge of capacitor C1 becomes zero. Mathematical models for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) of the proposed converter are explored. Furthermore, a dual PI controller is designed for the proposed converter to maintain a high fixed output voltage. In addition, the PCB design and experimental testing of the proposed converter to verify the simulation and laboratory results. Specifically, the proposed converter is designed to boost up voltage (30–40 V) to a variable output voltage between 200 and 300 V at 300 W at efficiency 96.7%. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a low‐power transconductor‐capacitor (Gm‐C) filter with programmable cutoff frequency is designed for electroencephalogram (EEG), electrocardiogram (ECG), and surface electromyography (sEMG) biosignals. The second‐order Butterworth low pass filter (LPF) is designed as an interface between an instrumentation amplifier (IA) and an analog‐to‐digital converter (ADC). The proposed Gm‐C filter suppresses out‐of‐band components and also plays an anti‐aliasing role. With the variable transconductance based on flipped voltage follower (FVF), the cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz are obtained for EEG, ECG, and sEMG, respectively. This structure is highly accurate by using a robust and low‐power common mode feedback (CMFB). With 0.8 V supply voltage, the total power consumption of the filter is only 56 nW, 100 nW, and 221 nW for cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz, respectively. The proposed Gm‐C filter is simulated in TSMC 65 nm CMOS technology and occupies an area of 0.12 mm2. The figure of merit (FOM) of the proposed filter is equal to 1.9 pW/pole. [ABSTRACT FROM AUTHOR]

Due to the intrinsic limitations, for example, limited adjustment freedom, the traditional wireless power transfer (WPT) systems cannot maintain high efficiency under variable loading conditions. To well solve this problem, a family of general magnetically coupled resonant WPT (MCR‐WPT) compensation topologies composed of LCC‐C with an n‐stage LC structure, or LCC‐C(CL) n, is proposed in this paper. Under the guideline of the generalized structure, some existing topologies are derived for verification, with new topologies established with unique advantages. From the LCC‐C(CL) n structures, a suitable topology can be selected to achieve a desired design purpose, such as constant voltage transmission, constant current transmission, or high‐efficiency transmission. Prototype experiments and comparisons are conducted in this work, which demonstrate the effectiveness and applicability of the proposed LCC‐C(CL) n MCR‐WPT converter family and the parameter design method. Experimental results also show that the new topology can maintain high‐efficiency power transfer for a wide range of loads. Even under light loading conditions, the power transfer efficiency is 30% higher than the traditional benchmark topology. The proposed WPT approach will have wide applications for on‐road wireless electric vehicle charging. [ABSTRACT FROM AUTHOR]

Summary: In this paper, irregular 32 pulse density modulation (PDM)‐controlled wireless power transfer (WPT) system is proposed for constant current (CC) and constant voltage (CV) outputs. The proposed WPT system has a load independent ZPA frequency characteristic with CC and CV outputs. Thus, soft switching conditions are achieved for both CC and CV outputs. An experimental prototype was prepared to validate the effectiveness of the proposed irregular 32 PDM‐controlled WPT system. WPT coil design parameters are presented and analyzed with lateral and rotational misalignment conditions in ANSYS. The experiments were determined as 3 A for CC output and 200 V for CV output. The maximum efficiency of the proposed system is measured (95.34%) at aligned coils with 100 mm air gap. In addition, the efficiency results are presented and evaluated by performing experimental studies under both lateral and rotational misalignment conditions. [ABSTRACT FROM AUTHOR]

Summary: This paper presents a new high voltage gain quasi Z‐source inverter consisting of a switched‐inductor unit. A coupled inductor including three windings is utilized in structure of the switched inductor in a way to increase voltage gain effectively. In addition, the configuration includes an active switch with low number of components that has positive effects on voltage gain and two of its components recycles stored energy of the coupled inductor similar to a clamp circuit. The converter boosts voltage appropriately in low shoot‐through duty cycles and transfers power with a continuous input current, leading to a reduction in losses, requiring smaller output filter and improving the efficiency. Also, the converter can operate in high modulation index for similar voltage gains compared to the other works which improves quality of outputs. Low number of components and fewer cores for inductors are considered during the design of the converter, causing some superiorities for it in comparisons. In addition, the presented converter has appropriate condition from the viewpoint of voltage stress on its diodes. To validate quality of the converter performance, a 240‐W prototype is prepared that converts 35‐ to 60‐V DC to three‐phase sinusoidal voltages where effective voltage of each phase is equal to 110 V. [ABSTRACT FROM AUTHOR]

Summary: In this paper, for standalone and grid‐connected PV systems, a three‐phase simplified split‐source inverter (SSI) is proposed and controlled using a model‐predictive control (MPC). The maximum power point tracking (MPPT) approach used is an incremental conductance method based on a PI controller for both systems. The standalone system is composed of PV modules, a three‐phase SSI, and a bidirectional power DC–DC converter that connects a battery bank and a DC‐side capacitor. The output AC voltages of SSI are controlled using MPC. The bidirectional power DC–DC converter regulates the DC‐link voltage (DCLV). The grid‐connected system consists of PV modules, a three‐phase SSI, and an AC‐side L‐filter. The DC‐link PI controller generates reference currents for the MPC algorithm. The MPC uses these reference currents to adjust and deliver the PV power to the grid while regulating the DCLV. The PI controllers' parameters are selected for both systems using the Harris Hawks optimization method. Both PV systems simulation results show that under various operating conditions, they have succeeded in fixing a DCLV and producing a high‐quality AC output voltage and current at low THD. Experimental results for the three‐phase standalone PV system used to verify the system's performance. [ABSTRACT FROM AUTHOR]

Variable supply clustered voltage scaling (VS‐CVS) is an effective way to decrease power consumption without compromising performance. One of the major challenges in VS‐CVS design is that level converting flip‐flops (LCFFs) not only need to have low power consumption but also high performance. In this paper, we propose two new structures of LCFF: the data branch sharing LCFF based on conditional charging (DBS‐LCFFCC) and the data branch sharing LCFF based on precharging (DBS‐LCFFP). The new structures adopt a data branch sharing scheme to improve the speed of the circuit as well as to reduce the number of transistors. Based on simulation results using HSPICE with PTM 32‐nm CMOS technology, the proposed LCFFs show an improvement of 19.2–67.2% and 41.6–76.3% in power‐delay‐product (PDP) at 50% data switching activity, respectively, compared to other advanced LCFFs. [ABSTRACT FROM AUTHOR]

Summary: In the context of the dual active bridge (DAB) bidirectional DC‐DC converter using the traditional dual‐phase‐shift (DPS) control method, a transient DC bias occurs during power co‐direction and commutation conversion. This bias negatively impacts the converter's transient performance and can lead to harsh effects, such as hard switching problems, resulting in power loss and excessive current stress. In a closed‐loop control system, poor transient response may destroy the stability of the converter. In this paper, the transient‐optimized‐dual‐phase‐shift (TODPS) control strategy is proposed to eliminate the transient DC bias and to maintain soft switching during transient states. It reduces power loss, eliminates excessive current stress, and allows for smooth transitions between single‐phase‐shift (SPS) and DPS control strategies without introducing DC bias. A closed‐loop control system based on TODPS control is established with feed‐forward compensation to adjust the primary‐side current and modify transmission power. This adjustment enhances the transient performance of the DAB converter. The proposed strategy is versatile and applicable to various power conversion scenarios involving DAB converters. It enables quick switching of the magnitude and direction of the primary‐side current during transient states, resulting in a smooth transient effect without noticeable overshoot or oscillation. The experiment results verify the effectiveness of the proposed transient optimization strategy. [ABSTRACT FROM AUTHOR]

Summary: Ultra‐high voltage inverters are widely used as grid‐connected devices in new energy grids, and the state‐space average model is the most practical modeling method for the inverter. However, the accuracy of this modeling method is significantly reduced because it ignores the high‐frequency switching process, which contains overshoot voltage and other factors that affect system stability. Moreover, the amplitude of the overshoot voltage in the ultra‐high voltage inverter will be huge, which may lead to the damage to switching devices, circuit overheating, and even the collapse of the system. Therefore, the wavelet decomposition and reconstruction methods are used in this paper to extract the transient characteristics of the inverter and integrate them into the state‐space average model. Compared with the traditional state‐space average model, the improved model method can obtain a more accurate overshoot voltage peak value with the same simulation step size. Then, it can provide a more precise reference for the withstand voltage in the device selection of a high voltage level system. The single‐phase full‐bridge inverter is taken as an example to illustrate the construction process based on the wavelet decomposition and reconstruction method. Finally, the simulation waveform is verified to be in good agreement with the experiment. [ABSTRACT FROM AUTHOR]

Summary: In recent years, the electric vehicle (EV) industry has developed rapidly, and research on wireless charging systems for the EV is very meaningful. This paper proposes a magnetic coupling resonant ultra‐high voltage EV wireless charging system based on parity‐time symmetry to meet the need of high transmission efficiency and high transmission power for the EV wireless charging system. Through the application of magnetic coupling resonance and parity‐time symmetry, the charging system can maintain constant transmission efficiency within a larger spatial range, which greatly reduces the high‐precision requirements for coil alignment. Through the proposed intelligent coil alignment system, the alignment degree of the power transmission coil, user experience, and energy transmission efficiency can be improved further, promoting the intelligence of the charging system. At the same time, an ultra‐high voltage booster module is added to the primary side of the system to provide high‐power input for the EV charging system. Simulation analysis and experiments verify the rationality and practicability of the charging system. Finally, the practical significance of the proposed system applied to power grid inspection work is discussed. [ABSTRACT FROM AUTHOR]

This paper discusses an alternative and Simulation Program with Integrated Circuit Emphasis (SPICE)‐compatible solution for the steady‐state simulation of power distribution networks. It introduces two alternative auxiliary subcircuits that allow to efficiently simulate the network in any simulation tool for circuit analysis. This feature introduces remarkable benefits in terms of simplicity and generality, since it avoids the need for any iterative method, thus bridging the gap between classical industry‐standard and general‐purpose simulators based on circuital equations, such as SPICE, and dedicated tools for the load flow analysis of power systems. The approach is first demonstrated based on a simple illustrative example, for which the performance in terms of accuracy and efficiency is discussed and then applied to the standard IEEE 33‐node power distribution benchmark. [ABSTRACT FROM AUTHOR]

The design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature. [ABSTRACT FROM AUTHOR]

Summary: In a wind energy conversion system (WECS) based on a doubly fed induction generator (DFIG), a fast and smooth automatic synchronization of the DFIG with the utility grid is always desirable. Additionally, elimination of the need for a speed encoder makes the synchronization process much more reliable. This paper proposes a modified voltage controller‐based automatic grid‐synchronization strategy for the DFIG‐WECS using a rotor‐current‐dependent model‐reference‐adaptive‐system (MRAS) for rotor‐speed/position estimation. A V/f control‐based starting strategy is used to start the DFIG. An improved decoupled DFIG stator voltage controller is proposed to enhance the transient response during the DFIG grid synchronization. The modified controller is implemented in a grid‐voltage‐oriented reference frame to synchronize the DFIG‐stator with the grid. A robust modified MRAS with higher noise immunity and reduced machine parameter dependency is used to estimate the rotor‐speed/position during synchronization control. To validate the performance of the proposed strategy, a DFIG‐based WECS is modeled and simulated using an OPAL‐RT real‐time simulator, where a motor‐generator setup is modeled to have an equivalent WECS configuration. As compared with the latest reported work, this approach reduces the synchronization time by 16.99% while ensuring a smooth synchronization with no stator inrush‐current, even without any speed/position encoder. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a novel two‐stage solution based on a 1‐MHz high step‐down hybrid LLC converter is proposed for low‐power 48 V voltage regulator modules (VRM). Since the hybrid LLC DCX converter with high step‐down ability is employed as the first‐stage, lower bus voltage can be obtained with the same transformer turns, which contributes to enhancing the duty cycle and efficiency of the second‐stage multi‐phase buck converter. Thus, an overall efficiency improvement can be achieved in the proposed two‐stage system, especially in low‐power applications. To further improve efficiency and power density, a novel integrated planar transformer is adopted for the double resonant tanks of the hybrid LLC converter. To validate the analysis, a 150‐W hardware prototype of the hybrid LLC converter is constructed in the laboratory. To ensure a fair comparison with existing LLC DCX designs, the output voltage is set at 6 V. The measured efficiency results of the first‐stage demonstrate an efficiency advantage at low power output levels compared to the similar full bridge LLC designs, especially at an output of around 100 W. Under the nominal 48‐V input, the first‐stage achieves a peak efficiency of 98.5% and a full load efficiency of 94.62%. Furthermore, a 4‐phase buck converter with nominal 6‐V input and 1.6‐V output is constructed to evaluate the efficiency performance of the overall system. When the second stage operates at 500 kHz, the proposed two‐stage system achieves a peak efficiency of 93.2% at 40A load, while maintaining an efficiency of 91.2% at 65A output. The calculated efficiency of the proposed two‐stage solution exhibits higher performance compared to the majority of single‐stage schemes. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a noteworthy compact dual‐band wireless power transfer (DB‐WPT) system is presented and studied. This DB‐WPT system is proposed using a capacitively loaded interdigital capacitor which reduces the size of the whole system, lessens the number of the attached surface mount elements, and accomplishes high efficiencies. An interdigital capacitor is printed in the ground plane of the design and loaded with a chip capacitor to produce dual bands. The operation of the system is verified by fabricating the proposed DB‐WPT system, which shows measured coupling efficiencies of 96% and 98.8% at 0.53 and 1.1 GHz, respectively at a transfer space of 12 mm. The fabricated structure has dimensions of 13.5 mm × 20 mm. The results show good agreement between the circuit model and the measurements. The idea of this design makes it applicable for compact near‐field WPT applications. [ABSTRACT FROM AUTHOR]

Summary: This paper investigates an improved space vector pulse width modulation (SVPWM) and channel‐decoupled method for dual‐channel permanent magnet synchronous machine (PMSM) powered by unbalanced battery packs. Recently, individual power supplied voltage source inverter (VSI) is introduced considering insufficient power rating and unsafe driving in electrical vehicles (EVs). However, the issues of strong coupling and unbalanced power supplies exist between channels. Firstly, a modular topology is constructed to improve the reliability and security of the system. Secondly, the channel‐decoupled method is introduced based on multi‐dq rather than the conventional vector space decomposition (VSD) to eliminate coupling among multi‐channel. Thereafter, the variable distribution of voltage vectors (VVs) is corrected by the proposed SVPWM, where the switch can be operated appropriately. Finally, the comparative experiments are carried out focusing on decoupling and unbalanced power supplies, and the results present superior performance in terms of low torque fluctuation and balanced channel currents. [ABSTRACT FROM AUTHOR]

Summary: The penetration level is limited by the occurrence of harmonic resonance under weakening grid. Under conventional current control, the penetrations with different power scheduling are assessed by the impedance Bode diagrams. To further suppress the current harmonics and improve the penetration with minimum cost, this paper proposes a distributed damping reshaping method by introducing the grid current feedback loop into the modulated wave of the inverter. The additional feedback loop is obtained by moving forward the feedback point of real damping link in hardware loop. Its equivalent control block has actual physical meaning, which helps to design damping coefficient. Further, instead of relying on the experience of engineer to select the damping coefficient, considering the effect of different values of damping on the inverter's performance, a damping design principle with the dual constraints on GCI's self‐stability and the global stability of the system is proposed. In detail, the range of the possible values of damping can be obtained by setting the desired system phase margin and the desired GCI's pole‐zero locations. In this range, the damping parameter, which remains the maximum ability of harmonic suppression for penetration improvement, can be determined by setting the desired damping ratio of the poles near the imaginary axis. Finally, simulations and experimental results were conducted to verify the correctness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

Summary: It is well known that DC‐DC boost converters are cascaded with DC‐AC inverters for grid connection of the photovoltaic (PV) systems. In the traditional control approaches, the mentioned DC‐DC and DC‐AC converters are controlled separately to facilitate the controller design problem. However, from the controller design viewpoint, the overall structure of the grid connected PV generator is a multi‐input multi‐output (MIMO) system. The duty cycle of the DC‐DC converter and inverter modulation index are the control inputs and, on the other hand, generated photovoltaic DC power and exported power to the grid are control outputs. Moreover, the inverter DC link voltage should be stabilized by the closed‐loop controller as well as an internal control output. If controllers are designed separately, it means that the interaction between DC‐DC and DC‐AC controllers isn't considered accurately, and since the isolated models of DC‐DC converter and DC‐AC inverter are extracted based on some approximated assumptions, separate controller design cannot guarantee stability and robustness of the whole system in a wide range of operation. To cope with these problems, in this paper, a novel MIMO sliding mode controller (SMC) is developed for comprehensive closed‐loop control of the DC‐DC boost converter cascaded with a single‐phase DC‐AC grid connected photovoltaic inverter. In the proposed approach, the dynamic model of whole system is developed comprehensively at first, and then, a unique MIMO controller is designed to control both DC‐to‐AC and DC‐to‐DC converters together. To cope with the nonlinear characteristic of the system and uncertainty of model parameters in a wide range, a fixed‐frequency SMC is developed using the comprehensive state space model of the closed loop system. In the proposed MIMO‐SMC controller, the AC power (which is exported to the grid) and operating point of the PV source are controlled via inverter modulation index and duty cycle of the DC‐DC boost converter, respectively. Another major advantage of the proposed system is mitigating the non‐minimum phase characteristic of the boost converter through the indirect control of inverter DC link capacitor. To evaluate the performance of the designed control system, simulation results are compared with a standard linear PI controller. It is shown that the developed system has zero steady‐state error and enjoys faster dynamic response during the start‐up and step changes of AC and DC current references. Moreover, it can maintain the stability of closed‐loop systems in a wide range of operations. [ABSTRACT FROM AUTHOR]

Summary: Ultra‐high voltage converters are usually employed to transform low voltage to high voltage in microgrids to produce renewable energy. However, it is challenging to develop control techniques due to the complicated structure of ultra‐high voltage converters and the numerous power switches and circuit components, which leads to poor dynamic characteristics of the system and a marked increase in fault rates. In order to understand the control theoretical characteristics of the ultra‐high voltage converter and provide a theoretical basis for circuit parameter analysis and control strategy design, this paper takes the boost converter cascaded system as an example to establish an accurate switching linear system model, discusses the control theoretical characteristics of the ultra‐high voltage converter in detail, and uses the decision theorem to draw the conclusion that the system is structurally controllable, reachable, and observable, simplifying the difficulty of analysis. The simulation and experimental findings show that the conclusion was drawn correctly. The research findings will give the boost converter cascaded systems modulation approach and circuit parameter design a theoretical foundation. [ABSTRACT FROM AUTHOR]