Search

Summary: This work proposes a link training based half‐rate dynamic current‐steering echo‐cancellation hybrid circuit topology for full‐duplex signaling that performs echo cancellation by deploying a bit error detection unit and backchannel adaptation. In addition, this work proposes a power‐efficient half‐rate dynamic current‐steering logic hybrid circuit for full‐duplex signaling over on‐chip interconnects for simultaneous transmission and reception. The half‐rate dynamic current‐steering hybrid circuit topology has low static power consumption compared with traditional current‐mode circuit topology implementations, thanks to the discrete nature of the current‐steering hybrid topology. The proposed scheme is implemented in 1.2 V, 65‐nm complementary metal‐oxide semiconductor (CMOS). The performance results show that the link training scheme sets the control bits for both the transmitter driver and hybrid circuit topology when the backchannel adaptation loop gets locked for 1‐ and 3‐mm interconnects for process, voltage, and temperature (PVT) variations. The proposed hybrid circuit topology is able to receive the required far‐end transmitted data with the link training scheme and has the differential recovered received signal voltage swing of 1.2 V for both 1‐ and 3‐mm interconnect at the 10‐Gb/s data rate. The total power consumption of the hybrid is 3 and 3.5 mW for 1‐ and 3‐mm interconnect with an energy efficiency of 0.6 and 0.7 pJ/bit, respectively, at 10‐Gb/s full‐duplex operation. [ABSTRACT FROM AUTHOR]

Summary: This work proposes a power‐efficient half‐rate current‐integrating logic (CIL) echo cancelation hybrid circuit topology for full‐duplex communication for off‐chip interconnects in 65 nm CMOS. The proposed hybrid topology has a low power consumption compared to traditional current‐mode hybrid circuit topology implementations, thanks to the CIL hybrid topology with sample and hold front‐end. The post‐layout performance of the half‐rate CIL hybrid includes package parasitic has a differential received signal voltage swing of 190 mV at 10 Gb/s data rate with a timing jitter of 16 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half‐rate CIL hybrid is only 2 mW, and its energy efficiency is 0.4 pJ/bit. The layout of the hybrid occupies an area of 0.0008 mm2. [ABSTRACT FROM AUTHOR]