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Colour graphics subsystems can be used in a variety of applications such as high-end business graphics, low-end scientific computations, and for realtime display of process control diagrams. The design of such a subsystem is shown. This subsystem can be added to any Multibus-compatible microcomputer system. The use of an NEC 7220 graphics display controller chip has simplified the design to a considerable extent. CGRAM (CORE graphics on Multibus), a comprehensive subset of the CORE graphics standard package, is supported on the subsystem.

The normal method of drawing in colour graphics systems with a number of memory planes is either to write separately on each plane or to write simultaneously on all planes. The first of these has the advantage of being flexible with respect to the number of memory planes, but it is very slow compared to the second. Writing simultaneously on all planes requires changes in basic drawing hardware for every addition to the number of memory planes. This paper attempts to introduce flexibility into the second approach: with the same basic drawing hardware and some external hardware, drawing can be performed on all planes simultaneously. The extra hardware does not demand any changes in the circuit timing parameters. A large portion of the extra hardware can be put on a programmable array logic (PAL) chip. The paper also presents an overview of an implementation of this approach, using the 82720 graphics display controller.

A low-cost Multibus-compatible graphics generator has been designed for a resolution of 512 × 512 pixels with a 3-bit colour code per pixel. The heart of the system is an 82720 graphics display controller (GDC). Usual designs of colour graphics generators use three different memory planes, each containing information corresponding to one of the three primary colours of the cathode ray tube (CRT). However, this approach requires a large PCB area and a large number of memories and transceivers. Further, the design does not use the full speed of present-day dynamic RAMs, as the three planes are read in parallel during display. In the scheme presented in this paper, the memory is partitioned into segments, three of which store graphics information corresponding to three colours. The three segments are read sequentially within each GDC read cycle, using the full speed of the dynamic RAMs. Moreover, memory segmentation reduces the chip count and PCB area considerably. The system can produce a character display of 40 rows with 64 characters in each row, and can magnify any part of the display by a factor of up to 16.