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GaN device as one potential power electronics device has been gained much attention recently. One of the power conversion systems, ANPC inverter using GaN HEMT is potentially considered to be prospective usage of low loss and high efficiency. In this work, we demonstrate one optimised PWM scheme aims at balancing the device electro-thermal stress based on Parma PWM to control 3-Level ANPC GaN inverter. The method is to decrease the loss for switches account for the large loss and increase the loss for switches with less thermal stress initially. The simulation and experimental results prove the effectiveness of the optimised PWM in controlling the loss distribution.

This paper investigates the static and dynamic temperature sensitive electrical parameters (TSEPs) for both SiC and GaN transistors. It is shown that both the qualitative and quantitative temperature characteristics of these parameters are various when different type of transistors are concerned. This finding can be used to select the most appropriate temperature sensitive parameter for the device under specific situation. In this paper, two types of transistors, SiC SCT2080KE MOSFET and GaN PGA26E19BA HEMT are evaluated and compared in terms of six TSEPs, including source-drain reverse bias voltage (VSD), static on-resistance (RDS,ON), gate threshold voltage (VGS(TH)), transconductance (gm), dIDS/dt switching transients and gate current (IG). Then, these TSEPs are compared using four criteria: temperature sensitivity, linearity, material and the capability of on-line temperature monitoring

This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue.

This paper investigates the effect of negative gate bias voltage (VGS) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device’s ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.

This work aims to present an investigation on short-circuit (SC) failure behaviour of SiC Power MOSFETs due to the onset of thermal runaway. As inferable from experimental outcomes, it is related to the formation of hotspot, whose exact location is mainly unpredictable and dictated by device structure and design parameters non-uniformities. TCAD simulations were performed to examine the impact of some parameters mismatch on hotspot formation and failure occurrence

An application-oriented integration concept for a half-bridge switch assembly has been developed based on the latest generation 70- μm-thin insulated gate bipolar transistors and diodes, which are rated at 600 V/200 A. This paper addresses the design and reliability of the assembly, with a fully bondwireless approach using cylindrical copper bumps. Advanced numerical structural simulation techniques are also applied to assess the influence of interconnect characteristics (material, size, and shape) and try to determine an optimum solution for reducing the stress and creep strain development in the solder joint. Preliminary experimental tests of the power module are also carried out at different switching frequency and loads to prove the validity of the proposed solution in terms of electromagnetic performance.

This paper presents an in-depth investigation into the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs comprising of functional as well as structural characterization and the corresponding underlying physical mechanisms responsible for device failure. One aspect of robustness for power MOSFETs is determined by its ability to withstand energy during avalanche breakdown. Avalanche energy (EAV) is an important figure of merit for all applications requiring load dumping and/or to benefit from snubber-less converter design. 2D TCAD electro-thermal simulations were performed to get important insight into the failure mechanism of SiC power MOSFETs during avalanche breakdown.

The behavior of Silicon Carbide Power MOSFETs under stressful short circuit conditions is investigated in this paper. Illustration of two different short-circuit failure phenomena for Silicon Carbide Power MOSFETs are thoroughly reported. Experimental evidences and TCAD electro-thermal simulations are exploited to describe and discriminate the failure sources. Physical causes are finally investigated and explained by means of properly calibrated numerical investigations, and are reported along with their effects on devices short-circuit capability.