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Low-drop-out (LDO) voltage regulators have been widely used in the power supply of the integrated circuits (ICs). With the evolution of the IC manufacturing process and its applications, the design of the analog controlled LDO has encountered more challenges in recent years. This paper starts with the discussion of low supply voltage and low output capacitor problems that have been found in the analog controlled LDO. To solve the mentioned problems, a novel design concept of the digitally controlled LDO is then presented. To verify the feasibility of the real implementation, the designed circuit is validated using the NanoSim/VCS software in a 0.18µm manufacturing process before the circuit is taped-out. With the test condition of 1V supply voltage, the stability of the proposed LDO is guaranteed when a small output capacitor (1µF) with very low equivalent series resistance(1mΩ) is used. Load test result shows that the output voltage spike is only 40mV with 3µs recovery time when the load current steps-up from 1 to 51mA.