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In this brief, a standard cell library targeting ultra-low voltages (ULVs) is designed in a 65-nm low-power CMOS technology to enable digital integrated circuits (ICs) to achieve good tradeoff among speed, power consumption, area, and reliability in the near/subthreshold region. The transistor sizes in the standard cells are optimized by threshold voltage tuning and technology feature exploration to enhance the switching and area efficiency of transistors. To balance the pull-up and pull-down networks, a Monte Carlo (MC) simulation-based balancing method is proposed. An AES-128 test circuit is fabricated by using the proposed library, achieving a minimum voltage of 0.338 V. Compared to the state of the art, our test circuit reduces the minimum energy delay product (EDP) by at least $3.55\times $. [ABSTRACT FROM AUTHOR]

In this paper, a closed-form expression for estimating the minimum operating voltage ( V\mathrm{ DDmin} ) of D flip-flops (FFs) is proposed. V\mathrm{ DDmin} is defined as the minimum supply voltage at which the FFs are functional without errors. The proposed expression indicates that V\mathrm{ DDmin} of FFs is a linear function of the square root of logarithm of the number of FFs, and its slope depends on the within-die variation of the threshold voltage ( V\mathrm{ TH} ) and its intercept depends on the balance between nMOS and pMOS, which is mainly due to the die-to-die V\mathrm{ TH} variation. The proposed expression of V\mathrm{ DDmin} is validated by the simulation results as well as the silicon measurements. Finally, we discuss the dependence of V\mathrm{ DDmin} on the device parameters. [ABSTRACT FROM AUTHOR]

A conditional-boosting flip-flop is proposed for ultralow-voltage application where the supply voltage is scaled down to the near-threshold region. The proposed flip-flop adopts voltage boosting to provide low latency with reduced performance variability in the near-threshold voltage region. It also adopts conditional capture to minimize the switching power consumption by eliminating redundant boosting operations. Experimental results in a 65-nm CMOS process indicated that the proposed flip-flop provided up to 72% lower latency with 75% less performance variability due to process variation, and up to 67% improved energy-delay product at 25% switching activity compared with conventional precharged differential flip-flops. [ABSTRACT FROM AUTHOR]