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Recent advances in resistive random access memory (RRAM) as high density, low power, and faster memory systems drive the need for devising a more lightweight integrity checking system for RRAM. In this paper, we design a new tag generation system for integrity checking of RRAM. A single read operation to a crossbar RRAM in the presence of sneak path currents can output a tag for the memory data that can be used for integrity checking. An analytical approach to model such a tag generation process is described in this paper. Security results predicted by the analytical model provide various design options leading to an optimal system from the perspective of considered security properties. The proposed design is simulated to investigate and verify the security properties of the system for a number of optimal design options predicted by the analytical model. Reliability of the proposed system is also measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage. Finally, the performance of the proposed system is compared against another existing lightweight tag generation method from the perspective of energy consumption, transistor count, and delay. [ABSTRACT FROM AUTHOR]

This paper presents a frame-interleaved low-density parity-check (LDPC) decoder architecture with a new interconnect partitioning scheme and time-distributed Min-Sum decoding schedule. The architecture exploits the cyclic structure of the parity-check matrix by unrolling each check node update in time over all connected variable nodes in order to minimize wiring complexity and power. Multiple frames are interleaved to maximize hardware utilization, while coarse-grained clock gating is used to systematically turn off inactive logic and memories to save power. To demonstrate the scalability of the proposed architecture, a multirate LDPC decoder test chip was fabricated for the IEEE 802.11ad standard in the 28-nm CMOS technology node. The design occupies an area of 1.99 mm2, contains 160 Kb of embedded static random-access memory, and achieves a throughput of 6.78 Gb/s at 10 decoding iterations for all four code rates specified in the standard. With early decoding termination, the fabricated chip consumes between 104 and 279 mW of power at a target bit error rate of 10−6 under nominal operation at 0.9-V supply and 202-MHz clock rate, resulting in an energy efficiency between 1.53 and 4.12 pJ/bit/iteration. With clock-frequency and voltage scaling, the fabricated chip achieves an energy efficiency between 1.1 and 3.1 pJ/bit/iteration. This paper achieves the highest normalized energy efficiency among recently published CMOS-based decoders for the IEEE 802.11ad standard at nominal clock frequency and supply voltage. [ABSTRACT FROM AUTHOR]

Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around −52 to −55 dB at Nyquist input. Then, a tap-interpolating fractional delay filters-based digital background time skew calibration technique is proposed. Also, a full analysis of the effects of the various parameters on the time skew generated spur levels is presented, which indicates that the time skew error level is related to the length of calibration filters, calibration range, and bandwidth penalty. The subchannel ADC exploits a 250-MS/s SAR ADC with a low-cost high-speed subradix-2 searching technique. The reference interference of nonbinary TI ADCs is discussed and tolerated by the subradix-2 searching scheme. The proposed adders-based encoding circuit is optimized with lower propagation delay to meet high-speed requirements. The prototype was fabricated in a 65-nm CMOS technology. The measurement results show that the ADC achieves a signal-to-noise-plus-distortion ratio of 49.6 dB with a power of 15.95 mW and a figure of merit of 63 fJ/conversion step when operating at 1-GS/s and 458.1-MHz Nyquist input. The ADC core achieves an area of 0.158 mm2. [ABSTRACT FROM AUTHOR]

Many applications show tolerance to inaccuracies. These can be exploited to build faster circuits with smaller area and lower power. This is particularly true for the hardware accelerators in heterogeneous computing systems. A major problem with approximate computing is that the resulting approximated circuit is highly dependent on the training data. Previous works often rely on static training results. If the workload is dynamic in nature or changes over time, output errors may reach unacceptable levels. Therefore, dynamic control methods are needed to solve this problem. To address this issue, in this paper, we propose an approximate self-adaptive architecture that autotunes itself at runtime based on the workload. Two different control mechanisms are proposed, one based on a regular heartbeat (HB), which resets the approximate circuits at regular intervals and the other based on internal lightweight checkers (LWCs). These checkers detect a change in the workload and reset the approximations. Experimental results show that our proposed methods work well leading to very good results compared to other approximation methods while keeping the output error within the given maximum error threshold at relatively low-area overheads, on average 8% and 8.5% for HB and LWC method, respectively, and delay overheads 5.9% and 8.1%. [ABSTRACT FROM AUTHOR]

Polynomial multiplication is one of the most rigorous arithmetic construction of postquantum cryptosystems. Utilizing number-theoretic transformations, the product of such multiplication can be efficiently computed in quasi-linear time $O(n.lgn)$. Error detection schemes of number-theoretic transform (NTT) architectures are essential to ensure correct mathematical operations, improved security, and thwart active side-channel attacks mounted through faults. NTT is not only significant to post-quantum cryptosystems, but the structure is also valuable to the already existing security protocols, e.g., signature schemes, hash functions, and the like. This paper, for the first time, introduces new error detection schemes of NTT architectures, successfully detecting both permanent and transient faults. Our schemes are based on recomputing with negated, scaled, and swapped operands. We have implemented the proposed schemes on the application-specific integrated circuit (ASIC). Performance and implementation metrics on this hardware platform show acceptable hardware overhead. As our schemes provide acceptable complexity and high efficiency, they can be utilized in compact hardware implementations of constrained applications, e.g., deeply embedded architectures. [ABSTRACT FROM AUTHOR]

In this paper, we study the 1-selector-1-resistor (1S1R) cross-point resistive random access memory (ReRAM) array because of its high density, fast access time, and ultralow stand-by power. Specifically, we focus on an access scheme where a data line is parallelly accessed from multiple subarrays with multibits accessed per subarray. A direct implementation of such a scheme has high energy efficiency but lower reliability compared with a single bit per subarray baseline scheme. So this paper proposes a low cost multilayer approach to improve energy-efficiency of multibits per access scheme without compromising reliability. At the cell level, we show how proper choices of bit-line and source-line voltage and SET recovery help reduce error rate by ten times. At the system level, we propose a new rotated multiarray access scheme where the average error rate of every accessed data line is one order of magnitude lower than the worst case, making it possible to achieve block failure rate of 10^\mathrm -10 with a simple Bose, Chaudhuri, and Hocquenghem t = 4 code. We show that for a 1 GB 1S1R ReRAM, the proposed approach can reduce energy by 41% with 2% extra area while maintaining latency and reliability compared with the baseline system. [ABSTRACT FROM PUBLISHER]

This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor ( \mu \textP ) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 \mu \textW to experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600 $000\times $ higher density than other non-FG approaches. [ABSTRACT FROM AUTHOR]

Spin-torque-based quantum computing (QC) architecture is emerging as one of the novel technologies to meet scalability challenge due to its intra architecture spin qubit state manipulation. The existing model for spin-torque-based QC does not include the ratio of reflection barrier height to exchange interaction to the transmission coefficients. Therefore, in this paper, a modified matrix is proposed to analyze the effect of ratio of reflection barrier height to exchange interaction on electron–qubit interaction, deviation of axis of rotation for single-qubit rotation, and average error probability for two-qubit rotation in a spin-torque-based ${n}$ -qubit reconfigurable architecture. In addition, the conventional and reduced quantum gates are compared for existing and modified matrices. The quantum gates performance is analyzed in terms of number of electrons required per gate for the electron–qubit interaction, gate fidelity, number of elementary quantum operations per gate, and gate execution time. Reconfigurability is accomplished through barrier height modulation to reduce the architecture hardware. Moreover, a novel nanomagnet-based spin reservoir is incorporated in the architecture for the nonlocal spin injection to facilitate only spin-based operations. High fidelity (~99%) of quantum gates is attained for the fault-tolerant QC. [ABSTRACT FROM AUTHOR]

This paper describes a low-power 1-GHz 4-bit time-domain arithmetic logic unit (ALU) targeting hardware accelerator. This ALU relies on the time-domain computation based on digital-to-time converter, digitally controlled oscillator, time-to-digital converter, and successive approximation register analog-to-digital converter. The interconnect bandwidth limitation addressed by the time-domain and voltage-domain encoding to improve the spectrum efficiency by $8\times $ . Encoder and decoders are part of the computation, and that results in 1-GHz operational speed in 65-nm CMOS consuming 17.75 mW only. Compared to the conventional approach, the proposed time-domain computation achieves significantly lower power and latency for similar area and resolution. [ABSTRACT FROM AUTHOR]

QR decomposition (QRD) has been a vital component in the transceiver processor of future multiple-input multiple-output (MIMO) systems, in which antenna configuration will be more and more flexible. Therefore, the QRD hardware architecture in the future MIMO systems should be more flexible to meet various antenna configurations. Unfortunately, the existing QRD hardware architectures mainly focus on the matrix of one or several fixed sizes. This paper presents a new triangular systolic array QRD hardware architecture based on parallel tiled QRD algorithm to decompose an 8\times 8 real matrix. The designed hardware architecture is flexible and can be used in various MIMO systems, in which the number of antennas is smaller than 4. This paper also proposes a modified algorithm for the bottleneck operations of parallel tiled QRD algorithm to reduce the hardware overhead. To further reduce the hardware overhead, the Newton–Raphson algorithm is adopted in the proposed algorithm. The implementation results show that the normalized processing latency performance and the normalized processing efficiency performance of the designed QRD hardware architecture both are better than most of the existing QRD hardware architectures. To the best of our knowledge, the hardware architecture presented in this paper achieves the superior normalized QRD rate performance to the existing QRD hardware architectures. [ABSTRACT FROM PUBLISHER]

In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these dual-quality compressors provide higher speeds and lower power consumptions at the cost of lower accuracy. Each of these compressors has its own level of accuracy in the approximate mode as well as different delays and power dissipations in the approximate and exact modes. Using these compressors in the structures of parallel multipliers provides configurable multipliers whose accuracies (as well as their powers and speeds) may change dynamically during the runtime. The efficiencies of these compressors in a 32-bit Dadda multiplier are evaluated in a 45-nm standard CMOS technology by comparing their parameters with those of the state-of-the-art approximate multipliers. The results of comparison indicate, on average, 46% and 68% lower delay and power consumption in the approximate mode. Also, the effectiveness of these compressors is assessed in some image processing applications. [ABSTRACT FROM PUBLISHER]

This paper presents the optimization of an existing electrically eraseable programmable read-only memory (EEPROM) production test flow by means of thorough analysis of the faulty dice and the test flow, which leads to an increase in the yield, a significant decrease in test time, and a decrease in the dppm (increase in quality) level leaving the factory. In order to manufacture high quality and cost-effective EEPROMs suitable for automotive underhood applications, several topics must be taken into account. In addition to a high reliability EEPROM technology, the choice of an advanced memory architecture including error correction code and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production test flow must not only be able to screen out weaknesses in the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides, which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time-consuming. [ABSTRACT FROM PUBLISHER]

Quasi-cyclic low-density parity-check (QC-LDPC) codes are adopted in many digital communication and storage systems. The encoding of these codes is traditionally done by multiplying the message vector with a generator matrix consisting of dense circulant submatrices. To reduce the encoder complexity, this paper introduces two schemes making use of finite Fourier transform. We focus on QC-LDPC codes whose circulant submatrices are of dimension (2^r-1)\times (2^r-1) and the entries are elements of GF (2^p) , where p divides r , and hence, GF (2^p) is a subfield of GF (2^r) . These cover a broad range of codes, and binary LDPC codes are a special case. Making use of conjugacy constraints, low-complexity architectures are developed for finite Fourier and inverse transforms over subfields in this paper. In addition, composite field arithmetic is exploited to eliminate the computations associated with message mapping and reduce the complexity of Fourier transform. For a (2016, 1074) nonbinary QC-LDPC code whose generator matrix consists of circulants of dimension 63 \times 63 with GF (2^2) entries, the proposed encoders achieve 22% area reduction compared with the conventional encoders without sacrificing the throughput. [ABSTRACT FROM PUBLISHER]

Specialized architecture combined with near- and subthreshold voltage circuits emerges as a promising candidate to improve the energy efficiency in performing complex computing kernels in a resource-constrained device. One of the critical challenges in such design is the large delay variability across process, voltage, and temperature (PVT) variations. The in situ error detection and correction (EDAC) technique can potentially handle such variations; however, since existing techniques have targeted von-Neumann architecture and nominal voltage circuits, it becomes nontrivial to apply them on near and subthreshold voltage accelerators, many of which do not base on the von-Neumann architecture. In particular, those accelerators often have no instruction, making it difficult to use the popular instruction-replay-based error correction. To tackle this challenge, in this paper, we propose a novel in situ EDAC technique that utilizes dynamic, temporarily, and spatially fine-grained body swapping for error correction without instruction replay. Using the proposed technique, we prototyped a spiking neural network (SNN) sorter in non-von-Neumann architecture. The prototyped chip can successfully remove the worst-case margin and, thus, achieve 49.3% higher energy efficiency and 35.6% higher throughput compared to the baseline that operates with the worst-case margin. The proposed technique incurs only 4.1% silicon area overhead and requires no additional supply voltage. [ABSTRACT FROM AUTHOR]

A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial function evaluation for 3-D graphics applications is presented in this paper. The performance of the evaluation process is highly dependent on the design of the multiplication and squaring structure. A novel hardware implementation for polynomial evaluation is presented. The proposed approach compensates the complex multipliers by using DCM which reduces the hardware complexity. The DCM scheme performs complex functions with power-efficient and area-efficient approach. The multiplier reduces the hardware computational effort in the piecewise polynomial approximation with uniform or nonuniform segmentation. For large operand input size, a multiplier adder converter and a dedicated radix-4 squaring unit are also proposed. These units achieve the least power consumption compared to previous approaches with large input word size. Comparison with general purpose multiplication has shown reduction in power, and delay by up to 36%, and 50%, respectively. The proposed technique exhibits up to 93% saving in power consumption compared to the current traditional schemes. [ABSTRACT FROM AUTHOR]

Owing to the limited response time of liquid crystal displays (LCDs), the motion-blurring effect is a critical problem to overcome for LCD applications. Among the available motion-blurring reduction methods, frame-rate upconversion (FRUC) presents an outstanding performance; however, it also yields a high computational load, which causes a design challenge for a hardware-efficient FRUC engine running advanced specifications. In this paper, a hardware-efficient FRUC algorithm and architecture were proposed, comprising three core techniques: bidirectional 3-D recursive search (BD-3DRS), spatial and temporal motion vector refinement (ST-MVR), and spatial and temporal overlapped-block motion compensation (ST-OBMC). BD-3DRS provides an initial MV with minor computational overhead. Subsequently, ST-MVR refines the initial MV to generate a more accurate final MV. With this final MV, ST-OBMC has finely processed the interpolated block, especially for the textural smoothness across block boundaries. The experiment results indicated that compared with other sophisticated FRUC methods, computation was reduced by 80% with a minor degradation in a peak signal-to-noise ratio of less than 2%. The hardware architecture was realized using the CMOS technology, and the chip size was $1.20 \times 1.20$ mm2. The working frequency was 270 MHz with a power consumption of 128.08 mW. The maximum throughput was as high as 508 Mpixels/s, which can support a resolution of $3840 \times 2160$ from 60 to 120 Hz. Compared with other FRUC architectures, this paper has demonstrated superior hardware efficiencies in terms of area usage and energy consumption. [ABSTRACT FROM AUTHOR]

This paper uses a theoretical model to approximate the delay of different characteristic two primitives used in an elliptic curve scalar multiplier architecture (ECSMA) implemented on k input lookup table (LUT)-based field-programmable gate arrays. Approximations are used to determine the delay of the critical paths in the ECSMA. This is then used to theoretically estimate the optimal number of pipeline stages and the ideal placement of each stage in the ECSMA. This paper illustrates suitable scheduling for performing point addition and doubling in a pipelined data path of the ECSMA. Finally, detailed analyses, supported with experimental results, are provided to design the fastest scalar multiplier over generic curves. Experimental results for GF(2^163) show that, when the ECSMA is suitably pipelined, the scalar multiplication can be performed in only 9.5 \mus on a Xilinx Virtex V. Notably the design has an area which is significantly smaller than other reported high-speed designs, which is due to the better LUT utilization of the underlying field primitives. [ABSTRACT FROM PUBLISHER]

Voltage scalable decoupled SRAMs operating at a subthreshold region have various challenges, such as deteriorated read bitline (RBL) swing resulting in read sensing failure and degraded cell stability due to the half-select write. This paper proposes an equalized bitline scheme to eliminate the leakage dependence on data pattern and thus improves RBL sensing and its resilience against process, voltage, and temperature variations. In addition, we propose a fast local write-back (WB) technique to implement a half-select-free write operation. With hierarchical bitline architecture, it facilitates a local read and a subsequent fast WB action to secure the original data without performance degradation. A 16-kb SRAM test chip has been fabricated in a 65-nm CMOS technology and achieved the minimum operating voltage of 0.24 V with a read access time of 4.88 \mu \texts . [ABSTRACT FROM AUTHOR]

This paper analyzes the benefits of using half-unit-biased (HUB) formats to implement floating-point (FP) arithmetic under a round-to-nearest mode from a quantitative point of view. Using the HUB formats to represent numbers allows the removal of the rounding logic of arithmetic units, including sticky-bit computation. This is shown for FP adders, multipliers, and converters. Experimental analysis demonstrates that the HUB formats and the corresponding arithmetic units maintain the same accuracy as the conventional ones. On the other hand, the implementation of these units, based on basic architectures, shows that the HUB formats simultaneously improve area, speed, and power consumption. In addition, based on the data obtained from the synthesis, an HUB single-precision adder is $\sim 14$ % faster but consumes 38% less area and 26% less power than the conventional adder. Similarly, an HUB single-precision multiplier is 17% faster, uses 22% less area, and consumes slightly less power than the conventional multiplier. At the same speed, the adder and the multiplier achieve area and power reductions of up to 50% and 40%, respectively. [ABSTRACT FROM AUTHOR]

The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. Image and video compression algorithms, such as JPEG, MPEG, and so on, are particularly attractive candidates for approximate computing, since they are tolerant of computing imprecision due to human imperceptibility, which can be exploited to realize highly power-efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximation statically and are not adaptive to input data. For example, if a fixed approximate hardware configuration is used for an MPEG encoder (i.e., a fixed level of approximation), the output quality varies greatly for different input videos. This paper addresses this issue by proposing a reconfigurable approximate architecture for MPEG encoders that optimizes power consumption with the goal of maintaining a particular Peak Signal-to-Noise Ratio (PSNR) threshold for any video. Toward this end, we design reconfigurable adder/subtractor blocks (RABs), which have the ability to modulate their degree of approximation, and subsequently integrate these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder. We propose two heuristics for automatically tuning the approximation degree of the RABs in these two modules during runtime based on the characteristics of each individual video. Experimental results show that our approach of dynamically adjusting the degree of hardware approximation based on the input video respects the given quality bound (PSNR degradation of 1%–10%) across different videos while achieving a power saving up to 38% over a conventional nonapproximated MPEG encoder architecture. Note that although the proposed reconfigurable approximate architecture is presented for the specific case of an MPEG encoder, it can be easily extended to other DSP applications. [ABSTRACT FROM PUBLISHER]

Long polar codes can achieve the symmetric capacity of arbitrary binary-input discrete memoryless channels under a low-complexity successive cancelation (SC) decoding algorithm. However, for polar codes with short and moderate code lengths, the decoding performance of the SC algorithm is inferior. The cyclic-redundancy-check (CRC)-aided SC-list (SCL)-decoding algorithm has better error performance than the SC algorithm for short or moderate polar codes. In this paper, we propose an efficient list decoder architecture for the CRC-aided SCL algorithm, based on both algorithmic reformulations and architectural techniques. In particular, an area efficient message memory architecture is proposed to reduce the area of the proposed decoder architecture. An efficient path pruning unit suitable for large list size is also proposed. For a polar code of length 1024 and rate 1/2, when list size $L=2$ and 4, the proposed list decoder architecture is implemented under a Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology. Compared with the list decoders in the literature, our decoder achieves 1.24–1.83 times the area efficiency. [ABSTRACT FROM PUBLISHER]

This paper presents a highly digital calibration technique suitable for high-speed digital-to-analog converters (DACs). The proposed calibration method does not require an adjustment of on-chip analog voltages and can therefore be a favorable method in a deeply scaled nanometer process. The calibration utilizes that adding several redundant unit current cells to predetermined weight groups can be achieved with low hardware overhead, and choosing the best subset out of multitude of combinations leads to accuracy improvement. This paper proposes a two-step coarse–fine algorithm to choose the best subset for weight groups and analyzes the design tradeoff between the amount of redundancy and the expected yield via numerical simulations. To verify the proposed calibration method, a prototype 9-bit current-steering DAC has been implemented in 90-nm CMOS technology. The calibration algorithm is implemented as software to expedite the experiment. The measured results show that static linearity performance improves by $10.8\times $ when the proposed calibration technique is applied. When running the DAC at 5-GS/s sampling speed, similar performance improvement has been observed, achieving peak signal-to-noise-distortion ratio of 54 dB at low frequency and 8-bit linearity when generating sinusoid up to 1 GHz. [ABSTRACT FROM PUBLISHER]

Network-on-chip based many-core processors break the limitations faced with single-core processors, and can bring high performance, improved yield, and high reliability. They are widely considered as the most promising platform. One of the most important questions is: what kind of granularity of cores (in other words, the number of cores and the area of each core under specific area constraint of the chip) is the best for many-core processors? Performance is widely used as the most important metric to determine the choice, but recently, reliability and yield are also becoming the first-class constraints in many application domains. This paper presents a novel performance model by considering practical program style, including pipelined and parallel program styles, as well as intercore communication, and proposes a new metric combing performance, reliability, and yield of many-core processors to choose the core granularity. According to our paper, with a given area (300 \mathrmmm^2 ) and certain applications, the optimal result is obtained using $8\times 8$ mesh when all three factors are considered. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a time-based analog-to-digital converter (ADC) architecture combining a flash ADC and vernier time-to-digital converter (TDC) to achieve both high speed and high resolution. The flash ADC and vernier TDC are pipelined to increase the conversion speed. A charge-steering amplifier is used for low-power residue transfer. A common level adjuster is added to the output stage of the charge-steering amplifier to stabilize the output common level against process, voltage, and temperature variation. Moreover, the vernier TDC using a dynamic delayer enables low-power operation. An 8-bit ADC test chip fabricated with 65-nm CMOS technology had a high sampling frequency (900 MHz) and low power consumption (3.5 mW). The figure of merit was 32 fJ/conversion step. [ABSTRACT FROM AUTHOR]

The versatility of cellular nonlinear network (CNN) made it attractive in various scientific and engineering applications. The strength of solving problems using CNN comes from the fact that it deals with nonlinear dynamic systems. In this paper, feasible criteria for adaptive hardware approximation, automated method to switch between high and low precisions, is proposed to efficiently reduce energy consumption of a digital CNN. Two different criteria, state- and sign-dependent control, are presented and compared by simulating discrete-time CNN with various applications: image processing, associative memory, and scientific computing. Simulation results show that the state-dependent control is better suited for automatically introducing approximate computing in CNN accelerator. Even further, this control method allows more aggressive power reduction by stopping the computations for those cells in the saturation region of CNN dynamics for applications like associative memory. As a result, adaptive hardware approximation is effective in reducing energy consumption of a digital CNN compared with simply injecting predetermined approximation for entire CNN computations. The experimental results also show that the acceptable level of energy reduction differs from the application, equivalently the type of CNN. [ABSTRACT FROM AUTHOR]

The STT-MRAM technology is a promising candidate for future on-chip cache memory because of its high density, low standby power, and nonvolatility. As the technology node scales, especially under 40-nm technology node, STT-MRAM cell design becomes a key issue to approach low power consumption, high access performance, and desirable reliability. The conventional 1T-1 magnetic tunnel junction (MTJ) and 2T-2MTJ cell designs cannot address these challenges efficiently. In this paper, we propose a novel 3T-3MTJ cell structure using the advanced perpendicular MTJ (p-MTJ) technology. It can store 2 bits with three MTJs. The differential sensing technique can be used to read out the most significant bit as fast as the 2T-2MTJ design. The sensing latency of 2 bits within the same cell is almost the same as the sensing latency of the 1T-1MTJ cell design. Therefore, the 3T-3MTJ cell can have the advantages of both 2T-2MTJ and 1T-1MTJ cells. Circuit-level simulations show that the proposed 3T-3MTJ cell structure can achieve a desirable tradeoff between storage density, access performance, and energy consumption compared to the prior 1T-1MTJ and 2T-2MTJ cell structures. Additionally, we propose a novel adaptive cache design based on the 3T-3MTJ cell structure, which can work in different modes to satisfy various memory access demands from different applications. Architecture level simulations validate the effectiveness of the proposed cache design. [ABSTRACT FROM AUTHOR]

In this paper, we present embedded dynamic random access memory (eDRAM)-based memory customization techniques for low-cost fast Fourier transform (FFT) processor design. The main idea is based on the observation that the FFT processor has regular and predictable memory access patterns, and it can be efficiently exploited for memory customization using eDRAM. The memory customization approaches are applied to both of the pipelined and memory-based FFT architectures. In the pipelined architecture, the read wordline (RWL) coupling write assist and data packing schemes are employed to reduce the redundant RWL and wordline driving, respectively, in column-interleaved memory arrays. The memory address decoder is also simplified with thermometer code by exploiting the sequential access patterns. For the memory-based architecture, the modified cached-memory structure is employed in addition to the techniques used in the pipelined FFT architecture. The hardware implementation results of 2k-point FFT with a 0.11- \mu \mathrm m CMOS technology show that the proposed eDRAM-based pipelined and cached-memory FFTs achieve 26.8% and 33.2% power savings over the static RAM-based FFT design, respectively. [ABSTRACT FROM AUTHOR]

Traditional network-on-chip (NoC) interconnects follow conventional packet switching architectures that require multiple cycles to traverse each router hop. In addition, commonly used NoCs lack low-latency multicast replication and acknowledgment aggregation mechanisms that are required to efficiently handle the collective communication requirements exhibited by many modern applications. To address these issues, the single-cycle multihop asynchronous repeated traversal (SMART) NoC architecture is proposed. By using an efficient router-bypass mechanism, the SMART NoC enables single-cycle data transfers even between physically distant on-chip routers. However, enabling single-cycle hops over long metal wires restrict the achievable clock frequency of the system. In other words, increasing the NoC clock frequency lowers the number of hops that can be bypassed in a single cycle in a fully wireline SMART NoC. In this paper, we demonstrate that by integrating on-chip wireless links, a novel look-ahead bypass-request mechanism and a congestion-free broadcast routing methodology, it is possible to enable low-latency and energy efficient data transfers in the SMART NoC even when the system is designed with high clock frequencies. For the various applications considered in this paper, the wireless-enabled SMART NoC achieves on an average 41% reduction in message latency compared to the wireline SMART NoC. This network level improvement translates into 20% savings in full system energy-delay product. [ABSTRACT FROM AUTHOR]

Clock skew minimization that is an important issue in very large scale integration design has become difficult due to the presence of process, voltage, and temperature (PVT) variations. The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even after a chip is manufactured has generated considerable discussion. The basic idea of the PST architecture is to minimize the clock skew dynamically. Unlike most previous works that have focused on the implementation and the performance issues of a PST architecture, this paper focuses on the testing issues of a PST architecture. However, testing the variation tolerance ability of the PST architecture is difficult because the clock skew does not directly affect the functionality of a design. In this paper, we propose an efficient fault model considering the physical limitation of the devices for the PST architecture. In addition, we propose some novel structures to detect the manufacturing faults and increase the robustness of a PST architecture. Our experiment shows that with a little increase in overhead, we can achieve robustness. [ABSTRACT FROM AUTHOR]

Koblitz curves are a class of computationally efficient elliptic curves where scalar multiplications can be accelerated using $\tau $ NAF representations of scalars. However, conversion from an integer scalar to a short $\tau $ NAF is a costly operation. In this paper, we improve the recently proposed scalar conversion scheme based on division by $\tau ^2$ . We apply two levels of optimizations in the scalar conversion architecture. First, we reduce the number of long integer subtractions during the scalar conversion. This optimization reduces the computation cost and also simplifies the critical paths present in the conversion architecture. Then we implement pipelines in the architecture. The pipeline splitting increases the operating frequency without increasing the number of cycles. We have provided detailed experimental results to support our claims made in this paper. [ABSTRACT FROM AUTHOR]

This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates, then uses these results to show how soft processor microarchitectures should be different from those of hard processors. We find that the ratios of the custom CMOS versus FPGA area for different building blocks varies considerably more than the speed ratios, thus, area ratios have more impact on microarchitecture choices. Complete processor cores on an FPGA use 17\--27\times more area (“area ratio”) than the same design implemented in custom CMOS. Building blocks with dedicated hardware support on FPGAs such as SRAMs, adders, and multipliers are particularly area-efficient (2\--7\times) , while multiplexers and content-addressable memories (CAM) are particularly area-inefficient (>100\times) . Applying these results, we find out-of-order soft processors should use physical register file organizations to minimize CAM size. [ABSTRACT FROM AUTHOR]

In this paper, a novel RRAM-based reconfigurable accelerator (R-accelerator) design is proposed, which makes special use of existing RRAM device for high-efficient reconfigurable application-specific computing. The proposed R-accelerator design consists of RRAM-based arithmetic unit (AU) array, fully integrated into commercial EDA design tools. A significant area saving is achieved compared with conventional digital counterpart due to the proposed logic contraction technique, as well as saving of storage space and routing congestions. For enabling the optimization of the AU array, this paper also proposes a systematical method on the synthesis of the AU array under routing channel constraint for application-specific designs. Two automatic mapping algorithms, including simultaneous mapping and incremental mapping algorithms, are proposed and compared. The experiments using 45-nm CMOS technology on a case study of dynamic time warping example and general benchmark programs show up to 49% area reduction and 28% performance enhancement using the proposed R-accelerator technique compared with conventional application-specified integrated circuit (ASIC) design. [ABSTRACT FROM AUTHOR]

In this paper, delay-locked loops (DLLs) used in dynamic random access memory (DRAM) are analyzed. DLLs can be categorized into digital- or analog-based topologies. This analysis starts with an explanation of technology trends regarding DLL for DRAM in the early 1990s and describes important DLL specifications and design approaches necessary for DLL use in DRAM: lock time, lock range, lock cycles, tDQSCK (DQS rising edge output access time from the rising edge of CK), and wake-up time from power down modes. DLLs have been widely used since 2000 to satisfy high operating speed requirements inherent in DRAMs. Finally, referring to studies published from 2000 to 2011, trends regarding power consumption, jitter, relationship between power and jitter, lock range, lock cycles, and wake-up time from power down are analyzed. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic RAM (STT-MRAM) is a promising memory technology for lower level caches because of its high density and nonvolatile nature. However, the high write latency is a bottleneck to its widespread adoption as the future on-chip memory. In this paper, we propose a new cache architecture—asymmetric write architecture with redundant blocks (AWARE)—that can improve the write latency by taking advantage of the asymmetric write characteristics of 1T-1MTJ STT-MRAM bit-cells. Due to the nature of the storage element in STT-MRAM, the time required for the two-state transitions (1\to 0 and 0\to 1) is not identical. In other words, one of the state transitions is slower than the other direction. In conventional cache architecture, the overall write latency is limited by the slower transition. However, the AWARE cache design introduces redundant blocks in each row, and they are preset to the initial state that enables the faster transition. Hence the write operations performed in these redundant blocks are much faster than the conventional write scheme. The write latency in AWARE is improved by 30% over conventional cache architecture with no area penalty in the data array. Moreover, the additional tag bits introduced in this technique result in <1\% penalty on the total cache area. In addition, the write energy increases modestly by 7% in the proposed cache design. However, this write-energy increase can be mitigated by sacrificing the cache capacity. [ABSTRACT FROM AUTHOR]

Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time. [ABSTRACT FROM AUTHOR]

In this paper, a novel radiation-hardened-by-design (RHBD) 12T memory cell is proposed to tolerate single node upset and multiple-node upset based on upset physical mechanism behind soft errors together with reasonable layout-topology. The verification results obtained confirm that the proposed 12T cell can provide a good radiation robustness. Compared with 13T cell, the increased area, power, read/write access time overheads of the proposed 12T cell are −18.9%, −23.8%, and 171.6%/−50.0%, respectively. Moreover, its hold static noise margin is 986.2 mV which is higher than that of 13T cell. This means that the proposed 12T cell also has higher stability when it provides fault tolerance capability. [ABSTRACT FROM PUBLISHER]

The Montgomery algorithm is a fast modular multiplication method frequently used in cryptographic applications. This paper investigates the digit-serial implementations of the Montgomery algorithm for large integers. A detailed analysis is given and a tight upper bound is presented for the intermediate results obtained during the digit-serial computation. Based on this analysis, an efficient digit-serial Montgomery modular multiplier architecture using carry save adders is proposed and its complexity is presented. In this architecture, pipelined carry select adders are used to perform two final tasks: adding carry save vectors representing the modular product and subtracting the modulus from this addition, if further reduction is needed. The proposed architecture can be designed for any digit size \delta and modulus \theta . This paper also presents logic formulas for the bits of the precomputation -\theta ^-1\bmod 2^\delta used in the Montgomery algorithm for \delta \leq 8 . Finally, evaluation of the proposed architecture on Virtex 7 FPGAs is presented. [ABSTRACT FROM PUBLISHER]

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultralow-power consumption. Previous works proposed mapping approaches to implement Boolean functions on SET arrays. However, these approaches were based on an ideal assumption that the SET arrays are defect-free. Recently, a diagnosis method was proposed targeting at defective SET arrays. However, the approach was static, such that the performance is inefficient. As a result, in this paper, we propose a dynamic diagnosis approach that can efficiently identify the locations and the types of the defects in the SET arrays. The experimental results show that the proposed dynamic diagnosis approach can achieve the same results as the previous work with much less CPU time on a set of benchmarks. Furthermore, the proposed method spent a few seconds while the previous work exceeded the CPU time limit of 3600 s on some benchmarks. [ABSTRACT FROM PUBLISHER]

Modern general-purpose graphic processing units (GPGPUs) have emerged as pervasive alternatives for parallel high-performance computing. The extreme multithreading in modern GPGPUs demands a large register file (RF), which is typically organized into multiple banks to support the massive parallelism. Although a heavily banked structure benefits RF throughput, its associated area and energy costs with diminishing performance gains greatly limit the future RF scaling. In this paper, we propose an improved RF design with bank stealing techniques, which enable a high RF throughput with compact area. By deeply investigating the GPGPU microarchitecture, we find that the state-of-the-art RF designs' is far from optimal due to the deficiency in bank utilization, which is the intrinsic limitation to a high RF throughput and a compact RF area. We investigate the causes for bank conflicts and identify that most conflicts can be eliminated by leveraging the fact that the highly banked RF oftentimes experiences underutilization. This is especially true in GPGPUs, where multiple ready warps are available at the scheduling stage with their operands to be wisely coordinated. In this paper, we propose two lightweight bank stealing techniques that can opportunistically fill the idle banks and register entries for better operand service. Using the proposed architecture, the average GPGPU performance can be improved under a smaller energy budget with significant area saving, which makes it promising for sustainable RF scaling. [ABSTRACT FROM AUTHOR]

The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current ( IW ), on/off-state resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}}$ / $R_{{\mathrm{\scriptscriptstyle OFF}}}$ ), and $I$ – $V$ nonlinearity ratio, interconnect material, and write/read scheme are systematically analyzed using a 3-D circuit simulation. The simulation results show that insufficient current drivability of the vertical transistor severely limits the number of 3-D layers. A low switching current (high $R_{{\mathrm{\scriptscriptstyle ON}}}$ ) or a high nonlinearity is beneficial for improving the write margin, while it degrades the read current sense margin. To alleviate this conflict, the read voltage needs to be boosted to the half write voltage. The common RRAM electrode material TiN is not suitable for the interconnect material due to a high resistivity. To improve write energy efficiency, a multiple-bit write scheme is proposed to reduce the write energy consumption per bit and enable a high bandwidth. With $R_{{\mathrm{\scriptscriptstyle ON}}}=500~\text{k}\Omega ( IW=6~\mu \text{A} ) and nonlinearity ratio =10 , 1-Mb 3-D vertical RRAM subarray is feasible to meet the specified write/read margin with $\sim 2$ -pJ/bit energy consumption. [ABSTRACT FROM PUBLISHER]

This paper proposes a complete and full automation framework of evaluating design rules (DRs) to facilitate the process of design technology co-optimization (DTCO), which is highly demanded in 14-nm and beyond technologies. Our proposed framework explores the changes of DRs and evaluates the impacts on the number and types of DR violations as well as the resulting cell/chip layout area. Precisely, the core engine of our DR evaluation framework for DTCO, the automatic cell layout generator, consists of key enabling techniques for standard cell layout optimization. They are integrated coherently to seamlessly support the advanced process technologies using FinFET transistors, complex DRs, and double patterning (DP) lithography. Also, the tight integration of our automatic cell layout generation into the DR evaluation framework with diverse analysis features enables the DTCO process to be much faster and more efficient. We provide a set of experimental data not only to show how much our proposed enabling techniques are effective in optimizing layouts but also to show how effectively our framework explores and analyzes the DTCO parameters (e.g., ground DRs and DP DRs). [ABSTRACT FROM AUTHOR]

Neuromorphic computing (NC) has acquired tremendous interest because of its ability to overcome the limitations of von-Neumann systems in data-intensive applications. NC systems are inspired from the human brain, which combine storage (synapse) and compute (neuron) to circumvent the memory bottlenecks in von-Neumann computing. The human brain consists of densely connected neurons, where each neuron can connect to thousands of synapses. Such dense connectivity enables hierarchical learning that enables high classification accuracies in NC systems, such as spiking neural networks (SNNs). Past research has focused on many-core architectures that implement synapses with memristive crossbars to overcome the memory bottlenecks and enable efficient compute. However, mimicking brainlike connectivity poses significant challenges. This is because the typical computation cores in a many-core architecture are connected with network-on-chip (NOC), which have high power consumption. In this paper, we propose a power line communication (PLC)-based architecture built with memristive crossbars for SNNs. PLC can use the on-chip power lines augmented with low-overhead transceiver to communicate data between neurons efficiently. Hence, PLC can enable dense connectivity required in SNNs while preserving the efficiency of memristive crossbars. We perform evaluations on SNNs ranging in scale from 1to 10 M synapses to demonstrate the efficiency of PLC-based NC system. We also propose a hybrid PLC–NOC-based design which can achieve high throughput along with high energy efficiency. [ABSTRACT FROM AUTHOR]

Ternary content-addressable memory (TCAM) designed using static random-access memory (SRAM)-based field-programmable gate arrays (FPGAs) offers a promising lookup performance. However, the update process in a TCAM table poses significant challenges for efficiently employing SRAM-based TCAM. SRAM-based TCAM for FPGAs is designed using block RAM or distributed RAM resources in FPGAs. Such designs suspend search operations during an already high-latency update operation, rendering them infeasible in applications that require high-frequency updates. This paper presents a dynamically updateable energy- and resource-efficient TCAM design (DURE) based on FPGAs. DURE exploits the distributed RAM resources in FPGAs. More specifically, the lookup table RAMs (LUTRAMs) available in SLICEM resources are configured as quad-port RAM, which constitutes the basic memory (BM) block in the implementation of DURE. The contents of the TCAM table are divided into chunks of equal size and mapped onto the LUTRAMs of the proposed BM blocks. DURE implements dynamic updates by reconfiguring the LUTRAMs of only those BM blocks that are associated with the word being updated, thereby allowing search and update operations to be performed simultaneously. This achieves a lookup rate of 335 million lookups per second, with an update rate of 5.15 million updates per second on a $512\times36$ size TCAM on a Virtex-6 FPGA. Compared with the existing SRAM-based TCAMs, DURE has a smaller single-cycle search latency and achieves at least 2.5 times more energy efficiency and a 67% higher performance per area. [ABSTRACT FROM AUTHOR]

This paper proposes a single instruction multiple data (SIMD) processor, which is programmed with high-level OpenCL language. The low-power processor is customized for executing multiple-input-multiple-output (MIMO) detection algorithms at a high performance while consuming very little power making it suitable for software-defined radio (SDR) applications. The novel combination of SIMD operations on a transport programmed multicore datapath allows saving power on both the execution front end and the back end, leading to very good energy efficiency with a compiler programmable design. We demonstrate the feasibility of the architecture with the layered orthogonal lattice detector and minimum mean-square-error MIMO algorithms, which can be used as a software-defined radio implementation of the 3GPP local thermal equilibrium r11 standard. Compared to other state-of-the-art SDR architectures, the proposed design adds features that improve programmer productivity with an insignificant power and area impact. [ABSTRACT FROM AUTHOR]

Emerging physical unclonable function (PUF) circuit designs in the IC supply chain pose not only a challenge to security threats but also a serious concern about hardware efficiency. The existing conventional PUF methods extract intrinsic random physical variation to generate two-valued secret key bits, which lack logical complexity and have poor efficiency in interconnect lines. This paper proposes a multiple-valued logic PUF circuit (MPUF), which focuses on adding logical complexity and minimizing hardware cost by processing on multilevel-cell and interconnect lines. The twins’ cell is selected as the MPUF cell to source the multiple-valued physical variation, and the bit-line sharing strategy was integrated to implement the four-valued PUF data. After full-custom designing, the MPUF with 512 cells only needs 16 transmit bit lines. The proposed MPUF chip is fabricated under 65-nm CMOS technology and the core area occupies approximately 0.016 mm2 with a 4.9- $\mu \text{m}^{2}$ bitcell size. The measured results show that the MPUF data passed National Institute of Standards and Technology randomness tests, and that it operates 0.1-pJ/b energy efficiency at 1.2 V, ensures randomness and uniqueness with 50.42% hamming distance, and less than 0.04 autocorrelation at 95% confidence level. Compared with other state of the arts, logical complexity improves 50% for resisting power attacks. [ABSTRACT FROM AUTHOR]

This paper presents a wideband frequency-translational resistive-feedback receiver (RX), operational from 0.1 to 2.2 GHz. Different blocker suppression techniques are proposed to improve both out-of-band (OOB) compression and weakly nonlinear distortion of the RX. The blockers are first rejected at the RX input using an $N$ -path filter. Then, a blocker current cancellation (BCC) technique is used to mitigate the effect of nonlinearity in the transimpedance amplifier. By introducing an auxiliary path in the RX, the OOB linearity of the RX is further improved by means of frequency-translational noise cancellation (FTNC) and split-BCC. The RX prototype fabricated in a 130-nm CMOS process achieves 2.6–3.2-dB noise figure (NF) and tolerates a 0-dBm blocker at a 50-MHz offset with an NF of 4.9 dB. At 40-MHz offset from the local oscillator (LO), the RX exhibits higher +23-dBm out-of-band input-referred inter modulation product of order 3 (OB-IIP3) without FTNC and higher +26 dBm OB-IIP3 with FTNC. [ABSTRACT FROM AUTHOR]

FinFETs have replaced planar MOSFETs due to their superior performance, power efficiency, and scalability. However, even FinFETs are expected to reach their scaling limits due to physical limits, process variations, and short-channel effects. As an alternative to device scaling, 3-D integrated circuits (ICs) can increase the number of transistors in a chip in the same footprint area. Among 3-D technologies, monolithic 3-D integration promises the highest density, performance, and power efficiency owing to its high-density monolithic intertier vias. A transistor-level monolithic implementation enables an independent optimization of transistor layers. However, it requires a new 3-D cell library. In this paper, we propose two new 3-D monolithic FinFET-based 8T SRAM cells and compare them with previously reported 6T and 8T SRAM cells implemented in 2-D/3-D. Both the proposed cells use pFinFET access transistors for better area efficiency in 3-D and low leakage current. One of the proposed cells utilizes independent-gate pFinFETs as pull-up transistors whose back gates are tied to the supply voltage for better writeability. This cell has 28.1% and 43.8% smaller footprint area, 31.6% and 43.2% smaller leakage current, and 53.2% and 29.0% lower read time compared with conventional 2-D 6T SRAM and 2-D 8T SRAM cells, respectively. [ABSTRACT FROM AUTHOR]

Feature matching is a fundamental step in many real-time computer vision applications such as simultaneous localization and mapping, motion analysis, and stereo correspondence. The performance of these applications depends on the distinctiveness of the visual feature descriptors used, and the speed at which they can be extracted from video frames. When combined with standard key-point detectors, the rotation-aware binary robust independent elementary features (rBRIEF) descriptor has been shown to outperform its counterparts. In this paper, we present a deep-pipelined stream processing architecture that is capable of extracting rBRIEF features from high-throughput video frames. To achieve high processing rate and low complexity hardware, the proposed architecture incorporates an enhanced moving summation strategy to calculate the key-points’ patch moments and employs approximate computations to achieve patch rotation. Multiplier-less circuitry is introduced throughout the architecture to avoid the use of costly multipliers. Implementation on the Altera Aria V device demonstrates that the proposed architecture leads to 53.3% reduction in hardware resources (adaptive logic modules), while achieving 50% higher accuracy (in terms of average Hamming distance) when compared to the state-of-the-art architecture. In addition, the proposed architecture is able to process high-resolution ($1920 \times 1080$) images at 60 fps, while consuming only 456.15 mW power. [ABSTRACT FROM AUTHOR]

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can automatically generate Verilog and SPICE netlists based on realistic FPGA configurations and a high-level eTtensible Markup Language-based FPGA architectural description language. The outputted Verilog netlists can be used to generate layouts of full FPGA fabrics through a semicustom design flow. SPICE simulation decks can be generated at three levels of complexity, namely, full-chip-level, grid-level, and component-level, providing different tradeoff between accuracy and simulation time. In order to enable such level of analysis, we presented two SPICE netlist partitioning techniques: loads extraction and parasitic net activity estimation. Electrical simulations showed that averaged over the selected benchmarks, the grid-/component-level approach can achieve $6.1\times /7.5\times $ execution speed-up with 9.9%/8.3% accuracy loss, respectively, compared to the full-chip level simulation. FPGA-SPICE was showcased through three different case studies: 1) an area breakdown analysis for static random access memory-based FPGAs, showing that configuration memories are a dominant factor; 2) a power breakdown comparison to analytical models, analyzing the source of accuracy loss; and 3) a robustness evaluation against process corners, studying their impact on energy consumption of full FPGA fabrics. [ABSTRACT FROM AUTHOR]