1. Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation.
- Author
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Ming-Yung Ko, Zissulescu, Claudiu, Puthenpurayil, Sebastian, Bhattacharyya, Shuvra S., Kienhuis, Bart, and Deprettere, Ed F.
- Subjects
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DIGITAL signal processing , *VERY large scale circuit integration , *DIGITAL communications , *FIELD programmable gate arrays , *PROGRAMMABLE logic devices - Abstract
In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression. [ABSTRACT FROM AUTHOR]
- Published
- 2007
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