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In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 [[micro]meter] 64 x 8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.

We report on two thermal characterization structures to measure the Seebeck coefficient [Alpha] of CMOS IC polysilicon thin films relevant for integrated thermal microtransducers. The test structures were fabricated using a commercial 1.2 [[micro]meter] CMOS process of Austria Mikro Systeme (AMS). The fabrication of the first structure relies on silicon micromachining. In contrast the second, planar, structure is ready for measurement after IC fabrication. The temperature dependent [Alpha] of the two polysilicon layers of the AMS process were measured with both devices. The agreement between the thermoelectric coefficients obtained with the two types of structures is better than 2.1 [[micro]volt] at 300 K.

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465 [degrees] C. For the Si films annealed at 750 [degrees] C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at [Lambda] = 405 nm), the potential barrier height [[Phi].sub.B] due to the grains, and the field-effect mobility, [[Mu].sub.n,p], of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called 'grains' of the films annealed at 600 [degrees] C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance.

Polysilicon buffered LOCOS (PBL) has been widely utilized for advanced isolation applications as moderately low lateral oxide encroachment may be achieved without defect formation. Unfortunately, PBL does not exhibit sufficient field oxide recess to support aggressive device scaling without introduction of processes which are difficult to control. Recently, polysilicon encapsulated local oxidation (PELOX) has been proposed as an easily scaled isolation technique that exhibits LOCOS equivalent recess. The integration of PELOX into an existing PBL 1 Mb DRAM baseline process is described. PELOX integrated PBL (PIPBL) is demonstrated to enhance final field oxide recess without increasing encroachment. The improved final field oxide recess is shown to provide increased process margin as evidenced by superior probe yield.