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A novel on-chip test circuit to measure single-event transient (SET) pulse widths has been developed and implemented in IBM 130-nm and 90-nm processes for characterizing logic soft errors. Test measurements with heavy ions and alpha particles show transient widths ranging from 100 ps to over 1 ns, comparable to legitimate logic signals in such technologies. Design options to limit the SET pulse width and hence to mitigate soft errors are evaluated with the test circuit to demonstrate the effectiveness of such design techniques. Index Terms--Alpha particle, combinational logic, guard rings, integrated circuit reliability, pulse width, radiation hardening, single event, single-event transient (SET), soft error, soft error rate (SER).

We report experimental results from noninvasive second harmonic generation (SHG) measurements applied to characterize separation by implantation of oxygen (SIMOX) and bonded thin film silicon-on-insulator (SOI) wafers. Results demonstrate that the SHG response of the SOI structure can provide an indication of the quality of the buried oxide interfaces, including roughness, charge states, and detection of the presence of metallic contamination. The potential application of SHG as a noncontact metrology tool for process control is described. Index Terms--Contamination, interface, metrology, nondestructive, roughness.

Structures integrated onto a BiCMOS test chip are specially designed to characterize the complex mechanisms related to proton radiation response in bipolar technologies. Bipolar devices from a commercial process are modified to include independent gate terminals. Through the use of gate control, the effects of proton-induced defects on discrete bipolar devices and analog bipolar circuits can be analyzed independently, thereby facilitating a quantitative description of the nonlinear relationship between the radiation defects and electrical response at both the device and circuit level. Index Terms--Base current, bipolar junction transistors, bulk traps, displacement damage, high-energy protons, input bias current, interface traps, ionizing radiation, oxide trapped charge, surface recombination.

Deposition of metallic impurities from HF process solutions has been investigated experimentally and explained theoretically in a qualitative manner. The depositions are shown to be electrochemical in nature in that an oxidation reduction reaction results in metal ions in solution depositing on the wafer as elements with an oxidation state of 0. The theory is only qualitative in that it can only predict which metals will deposit, not how much. Experimentally, simple transmission equations can be determined which relate metallic contamination levels on Si wafer surfaces (atoms/[cm.sup.2]) to metal concentration in the solution (ppb). Simple test structures have been fabricated with known amounts of iron and copper contamination in the pregate oxide clean of a 1.25 [[micro]meter] CMOS process. Device measurements indicate device degradation in the case of copper, confirming deposition studies that copper deposits from HF solutions. Iron contaminated wafers show no contamination related device effects, in support of theoretical predictions and deposition studies indicating iron does not deposit from HF solutions. The importance and potential usefulness of test structures as homogeneous contamination monitors is illustrated through device modeling of the contamination effects observed in the test structures that can then be used to estimate the effects of such contamination on ULSI circuit performance.