Search

The National Institute of Standard and Technology (NIST) is developing single-crystal reference materials for use as critical dimension (CD) reference materials. In earlier work, the reference features on these reference materials have been in the device layer of a silicon-on-insulator (SOI) wafers, with the buried oxide providing electrical isolation. This paper describes a new method of Slating the structures from the substrate by mews of a pn junction. The junction isolation technique is expected to provide several advantages over the SOI technique Including minimal susceptibility to charging when imaged in a CD scanning electron microscope (CDSEM), better edge quality, and ease of manufacture. Primary calibration of these reference materials is by imaging the cross-section of the feature with high-resolution transmission electron microscopy (HRTEM) at sufficiently high energy to resolve and count the individual lattice planes while electrical test structure metrology techniques provide the transfer calibration. Secondary calibration is performed with electrical test structure metrology, supplemented by visual techniques to verify that the features meet uniformity requirements. In this paper, we describe results for determining the electrical critical dimensions of these junction-isolated structures. This measurement and data analysis technique is a unique combination of the short-bridge variation of the cross-bridge resistor and the multi-bridge structure. [ABSTRACT FROM AUTHOR]