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Zero-voltage-switching (ZVS) has been widely applied in widebandgap devices based on high-switching-frequency converters, for instance, dual-active-bridge isolated dc–dc converter, which consists of two H-bridges. To secure ZVS for all eight switches, previous literature mostly focuses on half-bridge to analyze switching transitions, which, however, is rather incomplete due to ignoring the impact of modulation strategies and cannot fulfill all circumstances. In this letter, the whole H-bridge is used as a unit to analyze the ZVS transient process, addressing the ZVS setting in different modulation strategies. The minimal initial inductor energy to complete the ZVS process is also quantified, which in return can reduce the transformer current, thereby enhancing the efficiency. Furthermore, the accurate ZVS transition time is derived incorporating with the nonlinearity of switch output capacitance, which can be further used to set the dead-band time. An H-bridge prototype with SiC devices is built up to verify the theory proposed in this letter. [ABSTRACT FROM AUTHOR]

This paper proposes a family of multiport switched-capacitor multilevel inverter (SCMLI) topologies for high-frequency ac power distribution. It employs asymmetric dc voltage sources with a common ground that makes it ideal to be employed in renewable energy farms and modern electric vehicles. The proposed family of step-up SCMLI attains higher number of output voltage steps with optimum component count in comparison to several existing topologies. The problem of capacitor voltage balancing is solved as the capacitors are inherently charged to a finite voltage every half cycle. In-depth study on two staircase modulation strategies, namely, selective harmonic elimination and minimum total harmonic distortion (THD) scheme is presented with study on the variation of switching angles and THD with modulation indices under both schemes. Working principle and analysis are presented for the proposed family of topologies. Simulation outcomes are validated with experimental results under both the aforementioned modulation schemes with equal and unequal output voltage waveform steps. [ABSTRACT FROM AUTHOR]

This paper proposes a switched-capacitor multilevel inverter for high-frequency ac power distribution systems. The proposed topology produces a staircase waveform with higher number of output levels employing fewer components compared to several existing switched-capacitor multilevel inverters in the literature. This topology is beneficial where asymmetric dc voltage sources are available, e.g., in case of renewable energy farms based ac microgrids and modern electric vehicles. Utilizing the available dc sources as inputs for a single inverter solves the major problem of connecting several inverters in parallel. Additionally, the need to stack voltage sources, like batteries or supercapacitors, in series which demand charge equalization algorithms, are eliminated as the voltage sources employed share a common ground. The inverter inherently solves the problem of capacitor voltage balancing as each capacitor is charged to the value equal to one of the input voltage every cycle. State analysis, losses, and the selection of capacitance are examined. Simulation and experimental results at different distribution frequencies, power levels, and output harmonic content are provided to demonstrate the feasibility of the proposed multilevel inverter topology. [ABSTRACT FROM PUBLISHER]

This paper discusses the impact of small dc capacitance in a motor drive using a floating capacitor H-bridge topology. The proposed topology is intended for applications where variable frequency control is not required. Special attention is paid on investigating the second-order dc capacitor voltage ripples, whose influence on the induction motor as well as on the motor drive itself is of importance. This issue is addressed in this paper through rigorous mathematical formulations. It is found that by inverting the second-order dc ripple voltage using the conventional SVPWM, no harmful harmonics will be generated in the motor line voltage. This demonstrates the possibility of drastically reducing the dc capacitance of the proposed system. Induction motor as well as H-bridge performance with respect to different dc capacitance values is demonstrated by experiments, which lays the foundation for cost reduction and reliability enhancement of the proposed system. [ABSTRACT FROM PUBLISHER]

A dual-buck inverter (DBI) possesses no shoot-through worries and can boost efficiency by using power mosfet s. The main drawback of a DBI is the use of more inductors than in a traditional full-bridge inverter. This greater number of inductors decreases the power density and increases system cost. In this paper, a modified cascaded full-bridge DBI is proposed. It retains all the advantages of the conventional cascaded full-bridge DBI, possesses no shoot-through issues, and can be operated with no pulse-width-modulation dead-times. It can be implemented with power mosfet without reverse recovery issues of a body diode to boost efficiency. The cascaded modules in the proposed inverter share current limiting inductors. Therefore, the number of inductors and inductor footprints, the complexity of the circuit layout, required inductance, and magnetic volume can all be decreased. To show the advantages of the proposed inverter, detailed theoretical analysis and experimental results are provided. [ABSTRACT FROM PUBLISHER]

A solid state variable capacitor (SSVC) with minimum capacitor is proposed. A variable ac capacitor (with capacitance varied from 0 to $C_{{{\rm ac}}}$) is traditionally implemented by an H-bridge inverter and a large electrolytic dc capacitor, whose capacitance is 20 times of the ac capacitor's value, in order to absorb the ripple power pulsating at twice the line frequency (2 ω ripple power). The proposed SSVC system consists of an H-bridge and an additional phase leg connected to an ac capacitor with fixed capacitance $C_{{{\rm ac}}}$ and can reduce the dc capacitance to minimum value for absorbing switching ripples. The ac capacitor absorbs the 2ω component and theoretically can eliminate 2ω ripples to the dc capacitor completely. The total capacitor size is reduced by 13 times if same type capacitors (film) are used. Moreover, the proposed SSVC shows special advantages in terms of the switches’ current and voltage stress compared to other applications and the total device power rating is only 1.125 times of H-bridge. Since the proposed SSVC only has a small dc capacitor, a novel control system directly based on ripple power is also proposed to achieve stable dc voltage and fast dynamic response. Simulation and experimental results are shown to prove the effectiveness of the proposed SSVC with minimum capacitor. [ABSTRACT FROM AUTHOR]

This paper presents and compares control strategies for three-phase open-end winding drives operating in the flux-weakening region. A six-leg inverter with a single dc link is associated with the machine in order to use a single energy source. With this topology, the zero-sequence circuit has to be considered since the zero-sequence current can circulate in the windings. Therefore, conventional overmodulation strategies are not appropriate when the machine enters in the flux-weakening region. A few solutions dealing with the zero-sequence circuit have been proposed in the literature. They use a modified space vector modulation or a conventional modulation with additional voltage limitations. This paper describes the aforementioned strategies, and then, a new strategy is proposed. This new strategy takes into account the magnitudes and phase angles of the voltage harmonic components. This yields better voltage utilization in the dq frame. Furthermore, inverter saturation is avoided in the zero-sequence frame, and therefore, zero-sequence current control is maintained. Three methods are implemented on a test bed composed of a three-phase permanent-magnet synchronous machine, a six-leg inverter, and a hybrid digital signal processor /field-programmable gate array controller. Experimental results are presented and compared for all strategies. A performance analysis is conducted as regards the region of operation and the machine parameters. [ABSTRACT FROM AUTHOR]

In this paper, a novel modular cascaded multi-level converter with multiwinding high-frequency (MWHF) transformer is proposed for medium- or high-voltage applications. In the proposed converter, a cascaded H-bridge rectifier (CHBR) is connected directly with the input ac source while the traditional step-down transformer is no longer necessary. Then, an isolated dc-dc converter composed by a group of H-bridge converters and a MWHF transformer with high power density is used to isolate the dc buses produced by the CHBR. The equivalent circuit and mathematical model of the MWHF transformer and the high frequency (HF) converter are obtained firstly in this paper. Then, the voltage stability under unbalanced loads is analyzed and the naturally balance ability is verified. To accelerate the dc bus voltage balancing process, a voltage balance control algorithm based on energy exchange between different transformer windings is proposed that is realized by accomplishing the phase shift adjustment of the terminal voltages on different windings. Simulations and experiments are implemented to verify the performance of the proposed converter and voltage balance algorithm. [ABSTRACT FROM AUTHOR]

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor. [ABSTRACT FROM AUTHOR]

This paper presents a new circuit configuration of single-phase multilevel current-source inverter (CSI). In this new topology, a basic H-bridge CSI working as a main inverter generates a multilevel current waveform in cooperation with inductor cells connected in parallel as auxiliary circuits. Each inductor cell is composed by four unidirectional power switches with an inductor across the cell circuit. The inductor cells work by generating the intermediate level of the multilevel current waveform with no additional external dc-power sources. A simple proportional-integral controller is applied to control the intermediate-level currents of the multilevel output waveform. A five-level and a nine-level pulsewidth-modulation inverter configuration, with chopper-based dc-current sources, are verified through computer simulations. Furthermore, an experimental prototype of a five-level CSI is set up and is tested. The results show that the test circuit works properly to generate the multilevel output-current waveform with low output harmonics by using small size of inductors without any additional external dc-power sources, which proves feasibility of the proposed strategy. [ABSTRACT FROM AUTHOR]

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating Vdc/2 where Vdc is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of Vdc/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of Vdc /2, switch less compared to the H-bridges, which operate at a lower voltage level of Vdc/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions. [ABSTRACT FROM AUTHOR]

Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity, requiring a great number of power devices and passive components, and a rather complex control circuitry. This work reports a new multilevel inverter topology using an H-bridge output stage with a bidirectional auxiliary switch. The new topology produces a significant reduction in the number of power devices and capacitors required to implement a multilevel output. The new topology is used in the design of a five-level inverter; only five controlled switches, eight diodes, and two capacitors are required to implement the five-level inverter using the proposed topology. The new topology achieves a 37.5% reduction in the number of main power switches required (five in the new against eight in any of the other three configurations) and uses no more diodes or capacitors that the second best topology in the literature, the Asymmetric Cascade configuration. Additionally, the dedicated modulator circuit required for multilevel inverter operation is implemented using a FPGA circuit, reducing overall system cost and complexity. Theoretical predictions are validated using simulation in SPICE, and satisfactory circuit operation is proved with experimental tests performed on a laboratory prototype. [ABSTRACT FROM AUTHOR]