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In recent years, very high frequency (VHF) converter has attracted much attention. However, with rich parasitic parameters and complex resonance links, there are some great difficulties to the modeling of such systems. Taking the on-off controlled VHF resonant boost converter as an example, this paper presents an accurate modeling and analysis method that considers multiple parasitic parameters. First, the closed-loop VHF converter system is divided into a main network and a parasitic oscillation network. Then, based on the operation analysis, an equivalent circuit model characterized by a time-varying input voltage source and two variable duty-cycle controlled switches is proposed. It worth noting that both the time-varying input and the controlled switches take into account the influences of the parameters. Furthermore, the periodic approximate analytical solution of the output voltage in the on stage is obtained by using the equivalent small parameter method to the proposed circuit model. And then combining the solution of the parasitic oscillation network and on-off state switching conditions, the steady-state waveform of output voltage can be obtained quickly. Finally, a prototype with operating frequency of 21.44 MHz is built to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Like conventional two-switch leg converters, the three-switch leg converters also have short-circuit risks and a dangerous shoot-through current is generated if switches of the same leg are turned on simultaneously. In this article, a new dual-buck structure is proposed for three-switch leg converters. The proposed structure is reliable because of no shoot-through concerns and high quality of output waveforms can be obtained due to the reduction in pulsewidth modulation deadtime. Unlike the conventional dual-buck three-switch leg that uses many passive components such as four current limiting inductors and three external diodes, the new dual-buck three-switch leg uses only one current limiting inductor with two external diodes. To verify the performance, the proposed three-switch legs are used in single-phase dual-output inverter and detailed theoretical analysis, simulation, and experiments are performed. Both continuous and discontinuous modulation schemes are applied and it has been figured out that discontinuous modulation scheme can improve the dc-link voltage utilization in the common-frequency mode of operation. [ABSTRACT FROM AUTHOR]

The single gate driven series connected power device stack possesses the advantages of high compactness and low cost. However, research of its short circuit (SC) characteristic remains uncovered. This article fills this gap and points out that, with the single gate driver it has the potential of over-current limitation. Furthermore, based on it, an improved single gate driven silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfet) stack with strong antishort circuit fault capabilities is proposed. By adding auxiliary circuits to adjust the driving process of the single gate driver, the SiC mosfet stack can be automatically turned off in both SC conditions of fault under load and hard switch fault, while the normal working principle of the stack is not influenced. Neither active control nor overcurrent detection is required, which is the biggest merit of the proposed topology. Its design and analysis are presented in detail, followed by the validation by conducting simulations and experiments. [ABSTRACT FROM AUTHOR]

This letter presents a partial-bootstrap gate driver circuit for switching loss reduction and crosstalk mitigation. The proposed circuit is simple and no additional power supply or control is needed. The circuit structure and operating principles of the proposed gate driver are introduced. Three different operating modes of the proposed gate driver are presented. Finally, the experimental results are presented to validate the proposed gate driver. It is found that the proposed gate driver can greatly accelerate the switching process and reduce switching loss. The proposed gate driver can also generate a gradually decaying negative voltage during the turn-off process to suppress crosstalk. [ABSTRACT FROM AUTHOR]

This article presents an area-efficient and fast-transient capless low-dropout regulator (LDO) with satisfactory static and dynamic performance in the full load current range. Active-capacitor frequency compensation strategy with push–pull charging ability is employed to reduce on-chip compensation cap without degrading loop stability at light load and improve transient response speed simultaneously. Moreover, in order to drive this compensation capacitance, it makes use of an adaptively biased signal- and transient-current boosting error amplifier as well as transient enhancement circuit with nonlinear control to achieve high loop gain/bandwidth and slew rate. The proposed LDO is implemented in a 0.35-μm 5V-CMOS process and occupies an active chip area of 0.077 mm2. Experimental results demonstrate that it can deliver 100-mA load current at 200-mV dropout voltage (VIN = 2.7–3.3 V, Cload≤100 pF). It consumes 66-μA quiescent current at light load and can recover within 0.7 μs for load transient. The voltage spikes at the output, undergoing a maximum load current change, are controlled well below 260 mV and good line/load regulation is achieved synchronously. [ABSTRACT FROM AUTHOR]

Converter topologies such as current-source rectifiers and inverters require switching devices with bipolar voltage blocking and unidirectional current conduction capability. Recently available dual-gate GaN monolithic bidirectional switches (MBDSs) can mimic such self-reverse-blocking (SRB) behavior if the MBDS’ two gates are controlled accordingly, but thus need twice the number of gate signals and gate drive circuits. Therefore, we propose cascode-diode control (i.e., without additional sensing or gate drive circuitry) of one MBDS gate using a cascode configuration with a low-voltage silicon Schottky diode. The resulting SRB-MBDS features quasi-ohmic conduction characteristic and single-gate control. We provide static and dynamic measurements of a discrete proof-of-concept realization (600-V, 190-m $\mathrm{\Omega }$ GaN MBDS; 40-V, 10-A silicon Schottky diode) that demonstrate the proposed SRB-MBDS’ feasibility. [ABSTRACT FROM AUTHOR]

GaN power high-electron-mobility transistors (HEMTs), with their fast switching transients and poor overcurrent tolerance, require overcurrent protection (OCP) circuits that can respond in under $\text{0.5}\, \mu \text{s}$. Monolithically integrating digital and analog circuits with GaN power devices is enabled by recent advancements in high-voltage GaN integrationplatforms. Thus, integrated OCP designs can be used to reduce the protection response time, the area penalty, and the assembly complexity. This work presents the first fully integrated, senseHEMT-based GaN OCP integrated circuit (IC) with an adjustable current limit and programmable blanking time, suitable for a wide range of power applications. The IC, implemented on a 200-V GaN-on-Silicon-on-Insulator (GaN-on-SOI) process, contains a power HEMT with a senseHEMT for current sensing, a totem-pole-based gate driver, an analog comparator, and a set of logic circuits to enable high-speed closed-loop OCP. The fabricated design is tested in both a clamped switching setup and a 12–48 V boost converter. The minimum OCP response time is estimated to be 36 ns with $dI_{D}/dt\geq \text{30}\,\text{A}/\mu \text{s}$ , one of the fastest amongst state-of-the-art OCP circuits for GaN. [ABSTRACT FROM AUTHOR]

This article proposes a new low-impedance transient-current enhanced (LTE) buffer, which is applied for low-dropout regulator (LDO) with large off-chip capacitor. The LTE buffer is based on current-shunt feedback technique and two ac coupling networks, which can achieve an extremely low output impedance and high charging/discharging current of the gate of power transistor at load transient response, while maintaining low-quiescent current consumption under the full-load range. In addition to containing the LTE buffer, the proposed LTE-LDO employs recycling-folded-cascode amplifier as the error amplifier, which has the advantage of high loop gain, loop bandwidth, and current efficiency. Meanwhile, simple Miller compensation with a nulling resistor is employed for frequency compensation and a complete small-signal analysis under different load current conditions is given in this article. This design has been implemented in semiconductor manufacturing international corporation 0.18 $\mu$ m complementary metal–oxide–semiconductor process and the experimental results show that the quiescent current consumption is about 48 $\mu$ A, and the maximum current efficiency of the LTE-LDO is 99.976 $\%$. The measured transient response shows that under the condition of 1 $\mu$ F load capacitance, when the load current changes to 200 mA/100 ns, the output voltage change is 76 mV. [ABSTRACT FROM AUTHOR]

This article presents quick analytical prediction methods of switching loss, turn-on/off overvoltage, di/dt, and dv/dt for SiC metal–oxide–semiconductor field-effect transistor based on device datasheet. First, the switching process is analyzed and the simplification principles are discussed based on charge conservation and flux conservation. Second, the analytical equations of switching loss, turn-on/off overvoltage, di/dt, and dv/dt are derived. Third, experimental results under different operating conditions are presented to validate the proposed methods. It is found that the average prediction error is 10.11%. Finally, relationships between switching performance and different parameters, such as parasitic capacitance, parasitic inductance, dc-voltage, and load current, are analyzed and summarized based on the proposed prediction methods. [ABSTRACT FROM AUTHOR]

Gate-oxide degradation has been one of the critical reliability concerns of silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors (mosfets), which could be monitored through aging-sensitive parameters. In this article, an online gate-oxide degradation monitoring method for planar SiC mosfets is proposed by extracting gate charge time at a specific range of gate voltage. It is based on the findings that the input capacitances of planar SiC mosfets change significantly over gate-oxide degradation, which is theoretically analyzed and experimentally verified. The capacitance variations are converted into the gate charge time as the new aging-sensitive parameter. The new parameter measurement circuit is proposed and integrated into the gate driver module. The article results indicate that the new parameter varies noticeably with gate-oxide degradation and the difference of this parameter caused by junction temperature is much smaller than that caused by degradation. Besides, the parameter is immune to package degradation and load current. The condition monitoring method can be implemented online since the parameter is extracted during the off-state of SiC mosfet devices, which does not affect normal operation. The confirmatory experiment is carried out to verify the correctness of the proposed method. [ABSTRACT FROM AUTHOR]

For silicon carbide power mosfets, high dv/dt in switching may bring about a high level of electromagnetic interference. This letter shows that the dv/dt rate decreases at lower load currents. A dynamic dv/dt control strategy is then proposed for switching loss reduction in the whole operating range, by maintaining the dv/dt at the maximum acceptable level. The effectiveness of the proposed control strategy is verified by an experiment, showing that the total switching loss can be reduced by as much as 22% at 30% load. Furthermore, the simulation shows that a power loss reduction of 11.4% can be obtained for an electric vehicle converter which typically operates at light loads for most of the time. [ABSTRACT FROM AUTHOR]

This article introduces the negative feedback into the gate drive. It proposes a negative feedback active gate drive (NFAGD) for silicon carbide devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. An auxiliary P-channel mosfet is introduced to construct a negative feedback control mechanism. Due to the negative feedback mechanism, the proposed drive can automatically attenuate the disturbance from the complementary device of the phase-leg. Compared to conventional gate drives, the proposed drive can suppress the crosstalk without influencing the switching speed, thus enables coordinated optimization of gate voltage stability and switching behavior. This article analyzes the operation principle and then recommend the fundamental design principle for the proposed NFAGD. Finally, experiment results demonstrate the effectiveness of the proposed NFAGD. [ABSTRACT FROM AUTHOR]

This letter proposes a modified double-dual-boost (DDB) high-conversion-ratio dc–dc converter. The proposed converter is derived from the existing DDB converter by a simple yet effective circuit modification and inherits all the advantages of the existing DDB converter. In addition, the input and output can share a common ground due to the circuit modification, enabling the use of low-side gate drivers for all switching devices. When compared with the existing DDB converter, the proposed converter requires only one more capacitor, and the seemingly two inductors can be integrated into a single inductor. Thus, the overall magnetic volume is the same as the conventional converter. To validate the performance of the proposed converter, a 2-kW prototype was fabricated and tested. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

This letter presents a high-frequency boost converter using an accurate feedforward-path current sensor for the fast-load transient response. To operate with the switching frequency of up to 25 MHz, the proposed current sensor senses the inductor current with a fast-sensing response time of about 4.5 ns. It also provides more accurate sensing gain than previous current sensors. In addition, the adaptive on-time control method is used for the proposed converter to further enhance the transient responses. The converter has been fabricated using a 0.18-μm CMOS process with a total chip area of 1.3 × 1.12 mm. It achieves a fast-load transient of only 1 μs at a 400-mA load step, and peak efficiency of 91.5 and 88.2% at switching frequencies of 15 and 25 MHz, respectively. [ABSTRACT FROM AUTHOR]

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off-state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications. [ABSTRACT FROM AUTHOR]

In this letter, we comprehensively investigate the electrical properties of the 1200 V planner-gate 4H-SiC power metal–oxide–semiconductor field-effect transistors under the mechanical strains. Three kinds of strains, including the biaxial strain, uniaxial strain parallel to the gate channel, and uniaxial strain perpendicular to the gate channel, are applied using the wafer bending system. It is found that all kinds of compressive strains improve the drain current (Id) under the same gate voltage (Vg) and shift the threshold voltage (Vth) negatively, while the tensile strains decrease Id and shift Vth positively. The Vth shift mainly results from the strain modulated band structure in the poly-Si gate. Under the same overdrive gate voltage (Vov), biaxial strains merely change Id, while both the parallel and perpendicular uniaxial compressive strains enhance Id. The uniaxial compressive strain elevates the electron mobility in the inverted channel by repopulating more electrons into the valleys with a smaller conduction effective mass, which results in the current improvement. [ABSTRACT FROM AUTHOR]

The burst-mode control is one of the most effective methods to improve the efficiency of a converter at the light load condition, but it inevitably reduces the voltage conversion ratio of the converter. In this letter, we propose a slam control for improving light load efficiency of the boost converter while maintaining its voltage conversion ratio. The proposed control method applies the full duty–ratio to the switch during predetermined time, which significantly increases the light load efficiency and sufficiently boosts the output voltage. In addition, the quasi-resonant operation enables zero voltage switching at the switch; thus, reducing further switching loss. This slam control can be easily implemented by adopting “OR gate” to synthesize the slam carrier and switching carrier. The feasibility and effectiveness of the proposed control were verified by the experimental results from a 20-W prototype. The power conversion efficiency was increased by more than 20% at the light load condition. [ABSTRACT FROM AUTHOR]

With a reverse p-n junction in the gate stack design, this work demonstrates a 1.2 kV/25 A normally off p-n junction/AlGaN/GaN high-electron mobility transistor (PNJ-HEMT). Benefiting from the robust gate terminal, the PNJ-HEMT exhibits a large gate breakdown voltage of 18.2 V and a positive threshold voltage of 1.7 V, enabling a wide gate-bias window. Thereafter, with an applicable VGS of 10 V, the transient switching characteristics in nanosecond timescale (11.7-ns rise time and 10.5-ns fall time) and notable immunity to dynamic Ron degradation, as well as record-high dynamic breakdown voltage (1.62 kV) under transient overvoltage have been demonstrated. In particular, rugged reliability is validated after over 1-million times dynamic breakdown with a 1.5-kV peak overvoltage. To the best of our knowledge, this is the first demonstration of high-VGS (10 V) GaN HEMT's circuit-level operating capability with considerable reliability, and has well exceeded the VGS limit of 5–7 V in conventional p-GaN gate-terminal devices, thus possessing great potentials in high-power, high-frequency, and high-reliability applications. [ABSTRACT FROM AUTHOR]

The drain to gate capacitance (Miller capacitance) of SiC MOSFETs leads to the Miller effect during switching transients. The Miller capacitance in a phase-leg configuration causes the crosstalk, the interaction between the two complementary switches, and the Miller plateau during the switching transient. The Miller effect reduces the switching speed, reduces reliability, and increases electromagnetic interference. In this article, by injecting a mirror cancellation current, the effects of Miller capacitance are canceled. The proposed technique includes a two-stage sensing and injection network to compensate for the nonlinearity of the Miller capacitance. The proposed technique can suppress both positive and negative gate voltage spikes induced by the crosstalk and reduce the switching power loss with the increased switching speed. Because no external control signals are required in the proposed technique, it can work with almost all commercial gate drivers. The detailed design for this proposed technique is presented in this article. The proposed technique was validated with both simulations and experiments. [ABSTRACT FROM AUTHOR]

Series connection of SiC power MOSFET is an attractive approach to expand the blocking voltage of SiC devices, whereas the dynamic voltage balancing among the series-connected devices is the most critical challenge of the technique. In this article, a simple, fast, and cost-effective dynamic voltage balancing circuit of the series-connected SiC MOSFETs is proposed to suppress the voltage imbalance among the devices. The proposed circuit is composed of a resistor-capacitor (RC) snubber with a coupled inductor to effectively sense the voltage imbalance and add a compensated signal to the gate driving voltage. In the article, the operation principle of the proposed method is described in detail and the parameter selection of the circuit is given. Then the optimized layout of the circuit in a typical half-bridge SiC power module is proposed to reduce the stray parameters introduced by the coupled inductor effectively. The proposed method is verified by experiments under different conditions. Compared with a purely RC snubber balancing strategy, the capacitor can be significantly reduced. Since only passive components are required in the feedback loop, the proposed method demonstrates a reliable and straightforward approach to achieve equal voltage sharing of the series-connected devices. [ABSTRACT FROM AUTHOR]

When designing solid-state Marx modulators (SSMMs) with fast-rising nanosecond pulses, the gate-driving scheme for pulse discharge switches is one of the most important aspects to be considered. In this article, we propose a nanosecond current-loop gate-driving circuit for a synchronized fast gate drive of pulse discharge switches. The proposed circuit comprises an inverter, a current-loop cable, and discharge switch drivers. The inverter generates bipolar pulses that simultaneously provide driving power and fast triggering signals to all discharge switch drivers through the cable. The triggered discharge switch drivers rapidly turn on/off all discharge switches with accurate synchronization. In the inverter and discharge switch drivers, the fast gate-driving methods were used to overcome parasitic inductances and realize nanosecond operation. The concept and operational principles of the proposed gate-driving scheme are presented. To validate the performance and reliability of the SSMM using the proposed current-loop gate-driving circuit, a laboratory test on a 10-kV–70-A–50-kHz SSMM prototype was conducted, and the results were discussed. [ABSTRACT FROM AUTHOR]

The BaSIC(EMM) topology has been previously demonstrated to improve the short-circuit (SC) capability of 1.2-kV SiC power MOSFETs from 3.5 to 7.4 μs while producing a 17% increase in the net on-state resistance. However, a SC time of 10 μs could not be achieved. In this article, a systematic procedure for selection of the Si power MOSFET used in the BaSIC(EMM) topology is described based on information published by manufacturers of Si power MOSFETs in their datasheets. A tradeoff curve between the Si EMM drain saturation current at 150 °C versus its on-resistance at 25 °C is proposed in this article for determination of the best Si EMM product. The proposed methodology allowed identification of a superior Si EMM device. It was experimentally validated that a SC with-stand time of 11 μs, under a gate bias of 20 V applied to the 1.2-kV SiC power MOSFET at a drain bias of 800 V, was achievable with an increase in on-resistance of only 3.6%. These experimental results demonstrate a greatly improved tradeoff curve between SC time and increase in on-resistance. [ABSTRACT FROM AUTHOR]

The turn-off capability test for the single cell of power devices is of great significance to both the safe operation assurance and the destruction mechanism research. However, with present techniques, the device under test is supposed to be destroyed once the turn-off fault occurs. In this article, a robust nondestructive test scheme based on the multistage anode voltage detection for 4500 V single-cell turn-off capability of press-packed devices is proposed. Based on the proposed scheme, a single cell of IGCT is tested until a fault occurs. The result proves that a total bypass time is less than 100 ns for the 2200 V/5 A turn-off fault, and thus, the aim of nondestructive tests can be achieved with the proposed method. [ABSTRACT FROM AUTHOR]

In this letter, the dynamic Ron degradation mechanisms of the p-GaN gate HEMTs induced by off-state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including VTH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The VTH positive shift diminishes the drain current by shrinking the overdrive VGS, which however, can be compensated by a higher VGS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and VTH shift have a very slow recovery process. [ABSTRACT FROM AUTHOR]

As superjunction devices are scaled down to smaller dimensions, the gate ringing becomes more prominent in dynamic switching. The exact origin of superjunction MOSFET's gate ringing has not been so far identified as the conventional three-terminal measurement method cannot capture the dynamic behavior of the device, in particular the redistribution of charge between the different internal capacitive components in the superjunction structure. In this article, it is found that the gate ringing is highly related to the input capacitance. Specifically, by employing a TCAD model with a split gate method, the gate-to-source (CGS) and gate-to-drain (CGD) current are investigated during the dynamic transitions. The gate ringing is highly dependent on sum of the input capacitances (CGS + CGD) for the turn-on. In the case of the turn-off, however, the gate ringing is affected by the ratio of the input capacitances (CGD/CGS) and a lower CGS is desirable for a low gate oscillation. [ABSTRACT FROM AUTHOR]

Imbalanced voltage sharing during the turn-off transient is a challenge for series-connected silicon carbide (SiC) MOSFET application. This article first discusses the influence of the gate–drain discharge deviation on the voltage imbalance ratio, and its primary causes are also presented and verified by LTspice simulation. Accordingly, a novel active gate drive, which aims to compensate the discharge difference between devices connected in series, is proposed and analyzed. By only using the original output of the driving IC, the proposed gate drive is realized by implementing an auxiliary circuit on the existing commercial gate drive. Therefore, unlike other active gate drives for balancing control, no extra isolations for power/signal are needed, and the number of the devices in series is unlimited. The auxiliary circuit includes three subcircuits as a high-bandwidth current sink for regulating switching performance, a relative low-frequency but reliable sampling and control circuit for closed-loop control, and a trigger combining the former and the latter. The operational principle and the design guideline for each part are presented in detail. Experimental results validate the performance of the proposed gate drive and its voltage balancing control algorithm. [ABSTRACT FROM AUTHOR]

This letter proposes a voltage balancing method for series-connected power devices in an LLC resonant converter. Series connection of power devices can allow an LLC resonant converter to operate in high-voltage applications. One key problem of series-connected power devices is the voltage imbalance due to device parameter deviations and gate drive delays. To achieve voltage balancing, an auxiliary module (AM) is connected in parallel with each power device. Each AM consists of a capacitor and an auxiliary switch with an antiparallel diode. The AM operates as a clamping circuit and voltage among the series-connected power devices can be shared evenly if the AM capacitor voltages are well-balanced. The AM capacitors are charged during the asynchronous period of the series-connected power devices. The excess energy of AM capacitors can be released by the freewheeling current during dead time in an LLC converter. By assigning a pulsing gate signal to AMs with higher voltages in every switching cycle, the AM capacitor voltages can be balanced. The proposed method will not induce additional power loss and does not affect the normal operation of power devices. Experimental results are provided to verify the effectiveness and feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

This article presents a cascaded gate drive power supply configuration to reduce the common mode (CM) current in phase-shifted full-bridge (PSFB) converters. In such converters, there are at least two $dV/dt$ sources generated at different floating points associated to the parasitic capacitances of the isolated barriers of the gate drivers (power supplies, and control signal isolation units), which can increase the conducted electromagnetic interference perturbations. This article is focused on the analysis of a new gate drive power supply configuration, which reduces the CM currents that circulate in the control part of the switching cells. This improvement is achieved by modifying the impedance network of CM current pathways. Experimental results are provided to prove the effectiveness of the new gate drive power supply configuration on a PSFB converter based on SiC-MOSFET devices. [ABSTRACT FROM AUTHOR]

The online junction temperature monitoring of power devices is a viable technique to ensure the reliable operation of mission-critical power electronic converters. This article provides a potential approach for the junction temperature estimation of SiC MOSFETs based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with load current. First, the physical mechanism and the temperature dependence of the dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of the dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double-pulse tests. The experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of the dynamic threshold voltage of two SiC MOSFETs is approximately 5.2 mV/°C and 19.6 mV/°C, respectively. [ABSTRACT FROM AUTHOR]

In this article, a nonlinear controller for a grid-tied voltage-source converter (VSC) supplying a constant power load is introduced. The control law combines a feedback loop and a feedforward compensator. The feedback loop strategy uses a feedback linearizing method for compensating nonlinearities appearing in the VSC model. The performance in the presence of changes between two different values of constant power is improved by including a fast feedforward compensation. This compensator uses estimates of power load and its time derivative obtained from a nonlinear observer. The resultant strategy is validated via simulation and experimental tests. These experiments show that the proposed scheme performs in a very good way. [ABSTRACT FROM AUTHOR]

Advanced SiC planar-gate power MOSFETs have been successfully manufactured in a 6-inch commercial foundry with device structures optimized for operation with gate drive voltage of 10 V, compatible with gated drive voltage for Si superjunction products. The electrical characteristics of three advanced SiC MOSFET options are described in this article and compared with those of a state-of-the art Si superjunction MOSFET. The new advanced SiC power MOSFETs are demonstrated to exhibit superior on-state and switching losses with significantly better body-diode reverse recovery performance. Their short-circuit withstand time is also found to be significantly longer than typical commercially available planar-gate SiC power MOSFETs. These improved characteristics make the advanced SiC power MOSFETs suitable replacements for Si superjunction transistors to enhance high frequency circuit performance. [ABSTRACT FROM AUTHOR]

Online junction temperature (Tj) measurement enables robust power converter operations by providing overtemperature protection and condition monitoring of the power devices. For SiC MOSFETs, the real-time (Tj) information is especially critical as limited field data are available regarding the reliability. In this article, utilizing the turn-on delay time as temperature sensitive electrical parameter, an online (Tj) measurement is realized through an intelligent gate drive. Specifically, the turn-on delay time is translated into the pulsewidth of a digital signal through the conditioning/logic circuits. During (Tj) measurements, the adjustable gate resistance circuit is activated to improve the measurement sensitivity beyond 600 ps/°C. Using the high-resolution capture module (300-ps resolution) in the system microcontroller, this pulsewidth is measured and then converted to junction temperature with a resolution of <0.5 °C. A prototype is built to validate the online (Tj) measurement method. The switching test results show that the circuit is able to precisely measure Td,on and offers a good linearity/sensitivity for (Tj) estimation. In the continuous operation, the junction temperature of a decapsulated device using an infrared camera and (Tj) obtained from the circuit match well with <1 °C difference under various operating conditions. In addition, the gate-oxide degradation's impact on Td,on is considered for SiC MOSFETs, and an aging compensation scheme is discussed to maintain the measurement accuracy throughout the device's lifetime. It is shown that the proposed circuit provides an accurate real-time (Tj) measurement for SiC MOSFETs, which can be deployed to improve the power converters’ reliability. [ABSTRACT FROM AUTHOR]

This article investigates and compares various modulation methods and capacitor voltage-balancing algorithms of a modular multilevel converter for solid-state transformer applications. Characteristics of capacitor charging and discharging are analyzed for the existing single-step alternating voltage balancing and the conventional sorting algorithms with phase-shift (PS) modulation and nearest level control (NLC) methods. Based on the analysis, the single-step alternating algorithm leads to a low-frequency voltage ripple, while the conventional sorting algorithm introduces additional switching actions. To address these issues, two new voltage-balancing algorithms are proposed: a multistep alternating voltage-balancing algorithm, and a currentless sorting algorithm. The performance of the proposed algorithms with the PS and NLC modulation methods is comprehensively investigated and compared based on theoretical analysis and experimental results. The study results demonstrate the capability of the proposed methods to balance capacitor voltages while reducing the low-frequency voltage ripple and avoiding additional switching actions. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) devices enable more compact and efficient design of applications such as traction inverters and rectifiers. With miniaturization of power electronics, the volume and weight of heatsink or cold plate occupies a significant portion. So, thermal design, especially power loss evaluation, is crucial to the whole system. Analytical switching model based on datasheet parameters is usually adopted to evaluate devices’ switching loss due to its convenience. However, when applied on SiC metal-oxide-semiconductor field-effect-transistors (mosfets), turn-on waveforms of conventional analytical switching model show obvious discrepancy from experiments at both current rising and voltage falling stages. The transfer and capacitance characteristics from datasheet are responsible for that. Due to short channel effect and drain-induced barrier lowering, transfer characteristic during turn on period varies with different drain-to-source voltage vds. Cgd during actual turn on period is also different from that on the datasheet. So, considering the actual turn on process, dynamic transfer characteristic and Qgd are proposed and measured in this paper. After these modifications, switching-on waveforms of the analytical switching loss model match the experiments very well, and error of the estimated loss is less than 5%. [ABSTRACT FROM AUTHOR]

In this letter, a model that predicates the degradation of 4H-SiC power metal-oxide-semiconductor field-effect transistors under repetitive avalanche stress is proposed. Since positive charges are injected into the gate oxide interface of the JFET region, the gate-drain capacitance $(C_{gd})$ is chosen as the targeted parameter to quantify the avalanche induced degradation. The relationship between the increment of the $C_{gd}$ and the injected charge density is calculated and validated to demonstrate the rationale of the model. It is found that the increment of $C_{gd}$ has a linear relationship with the logarithm of the total avalanche energy (EAV) dissipated on the device. Excellent agreement is also achieved between the simulated degraded data and the measured one, further proving the accuracy of the proposed degradation model. [ABSTRACT FROM AUTHOR]

Considering the propagation delay, dVSW/dt immunity, and power dissipation issues in the bootstrapped high-side gate driver design, a monolithic high-voltage dc–dc buck converter with a high-speed dynamic level shifter and improved gate drive buffer is presented in this article. With the introduction of instantaneous dynamic current, the propagation delay of the level shifter is reduced to 1.13 ns for the high-side switch. The dVSW/dt immunity is enhanced by a dynamic current compensation during positive slewing and a diode voltage clamp during negative slewing. The average current consumption of the level shifter is only 8.45 μA at a switching frequency of 1 MHz. The proposed gate drive buffer eliminates the shoot-through current with the use of dead-time control. The compact level shifter and buffer are also used to drive an integrated p-channel mosfet transistor serving as a bootstrap diode emulator. Experimental results show that the fabricated converter with the proposed scheme regulates well with an 18 V input, 1.05 V output, and 2 A load current. Also, high efficiency of up to 93% is achieved. [ABSTRACT FROM AUTHOR]

Gallium nitride high-electron-mobility transistors (GaN HEMTs) exhibit dynamic on-resistance (d ${R_{\text{on}}}$), where the on-resistance immediately after turn-on is higher than the dc value at the same junction temperature. A proliferation of recent literature reports d ${R_{\text{on}}}$ , with some publishing an eight times increase in conduction losses and others finding that the problem is nonexistent. This variation can be largely attributed to the standardized double-pulse-test (DPT) method, which does not specify the blocking time and will ignore any effects that accumulate over multiple switching cycles. With no consistent measurements, designers are left without an accurate conduction loss estimate in converters with GaN HEMTs. We discuss the underlying causes of charge trapping to find the key influences over d ${R_{\text{on}}}$ , and show that the DPT technique gives invalid results. Our measurements validate that each operating parameter must be independently controlled and that only steady-state d ${R_{\text{on}}}$ measurements will predict in situ performance. For the commercial GaN HEMT tested in this letter, the worst-case d ${R_{\text{on}}}$ is nearly two times higher than the dc resistance at the same temperature, confirming that accurate d ${R_{\text{on}}}$ characterization remains critical to predicting converter characteristics. Finally, we provide a reporting framework for GaN HEMT manufacturers and methods to estimate conduction losses in converters with GaN HEMTs. [ABSTRACT FROM AUTHOR]

In an industrial-grade bus, transient voltage suppressor (TVS) devices that need to withstand inrush currents ensure electrostatic discharge (ESD) reliability of the core chip. This article designs four types of dual-direction silicon-controlled rectifier (DDSCR) device structures based on the 0.5-μm CMOS process. The ESD performance of the TVS device is predicted and verified based on the basic principles of the device, two-dimensional device simulation, and transmission line pulse test results. Four DDSCR structures are embedded with floating N+ to adjust the device's holding voltage window. The results show that the current release capacity of DDSCR_1 is 81.93 mA/μm. The current release capability of DDSCR_2, which has a double-dummy-gate structure, is 82.37 mA/μm. The current release capability of DDSCR_3 of the gate-controlled structure is 86.68 mA/μm. The current release capability of DDSCR_4 of the double-dummy-gate structure and the gate-controlled structure is 86.25 mA/μm. Furthermore, the effect of the size of these devices on the ESD characteristics was studied. The on-resistance of the device structure is calculated by the curve-fitting method. The influence of the dummy gate structure and the gate-controlled structure on the ESD characteristics is analyzed. Finally, the optimal device size to meet the window is found. [ABSTRACT FROM AUTHOR]

This paper proposes short circuit and overload gate-driver dual-protection scheme based on the parasitic inductance between the Kelvin- and power-source terminals of high-current SiC mosfet modules. The paper presents a comprehensive analysis of the two schemes in question, including worst-case analysis used to assess their parametric dependence due to manufacturing tolerances and temperature variations, as well as the in-depth design procedure that can be generally applied to any power module containing a Kelvin-source. For verification, a compact 1.2-kV, 400-A half-bridge module integrating the two protection circuits was developed. The results obtained demonstrate a response time within tens of nanoseconds, and effectively validate their functionality under short circuit and overload scenarios. Finally, a 100-kW, 400-V dc three-phase voltage-source inverter was used to demonstrate the gate-driver with integrated protection functions under 105°C ambient temperature conditions. [ABSTRACT FROM AUTHOR]

Single-input dual-output (SIDO) dc–dc converters have gained attention with the increasing need of multiple voltage levels. Magnetically coupled inductor SIDO (CI-SIDO) boost converter is the topology focused in this article. Ripples in inductor currents play important role in design of dc–dc converters and need to be as low as possible. The shift of one gate pulse with respect to another gate pulse has been used in converters, such as interleaved boost for reducing ripples. However, unlike interleaved boost, CI-SIDO boost has unequal output voltages and unequal inductances. The values of shifts, at which ripples are minimized, vary under different conditions of CI-SIDO boost. So, the analysis to reduce ripple in interleaved boost is not applicable for CI-SIDO boost. This article presents a detailed analysis of CI-SIDO boost converter for obtaining minimum ripples by shifting gate pulses. The analysis accounts for all permissible combinations of output voltages and inductances. Ranges of shifts in gate pulse are found, for all conditions, to achieve minimum ripple in each inductor current separately, and both inductor currents simultaneously. The practical applications of the analysis are shown by giving examples. The ranges found are verified by simulation in MATLAB/Simulink and experiments on laboratory prototype. [ABSTRACT FROM AUTHOR]

State-of-the-art silicon carbide (SiC) power devices provide superior performance over silicon devices with much higher switching frequencies/speed and lower losses. High switching speed is preferred for achieving low switching loss, yet high dv/dt and di/dt can result in high EMI emission during switching transients. These switching dynamics can be controlled by the device gate driving strategy. The multi-level active gate driver (AGD) approach is able to tradeoff the switching losses with the dv/dt and di/dt for each switching transient. A novel three-level (3-L) AGD for SiC power mosfet trajectory control is introduced. Its turn-off profile has a shorter turn-off delay compared to any existing methodology. Accordingly, a comprehensive datasheet-driven trajectory model for the online model-based optimization of the 3-L turn-off is introduced. The main factors that impact the 3-L turn-off performance are analyzed with this model. The experimental results of double pulse tests validate the approach. Additionally, the benefits of the proposed 3-L AGD method over two-stage turn-off and conventional gate drivers on the market are illustrated through experiments. [ABSTRACT FROM AUTHOR]

In this paper, a battery balancing circuit is proposed for the series-connected lithium-ion battery cells based on the principle of synchronous rectification. The proposed balancing circuit, also referred to as an equalizer, mainly includes a buck–boost converter (BBC), a multiport half-bridge converter (MHBC), and a driving circuit. The MHBC is coupled with a multiwinding transformer. Compared with the conventional congeneric methods, the number of transformer windings is almost reduced by half, leading to a more compact size and lower cost. Moreover, the secondary mosfets of the MHBC are synchronously driven by the primary half-bridge converter (HBC) without the need of additional isolated mosfet gate drivers and power supplies, dramatically reducing the circuit cost and complexity. In addition, the proposed equalizer can realize the module-to-multi-cell (M2MC) equalization under severe imbalance conditions to improve the balancing speed, and work at the any-cell-to-any-cell (AC2AC) self-balancing mode under slight imbalance conditions to improve the balancing efficiency and effectiveness, which achieves a good trade-off between balancing speed and effectiveness. The expressions of the equalization current and efficiency are derived and verified by experimental results. The proposed equalizer is experimentally evaluated for a string with 12 series-connected lithium-ion cells. [ABSTRACT FROM AUTHOR]

An output-capacitorless low-dropout regulator (OCL-LDO) using a dual-active feedback frequency compensation (DAFFC) scheme with both transient and stability enhancement has been presented in this paper. The DAFFC scheme consists of two parallel active feedback paths, which creates two pole-zero pairs to effectively enhance the stability and transient response for the proposed OCL-LDO. Compared to the conventional single-path active-feedback frequency compensation method, the proposed DAFFC technique has provided one more design freedom with one more active feedback loop deployed and has been proved to be capable of obtaining better compensation effects with the same capacitor budget. Besides, the induced extra ac currents by the two active feedback loops have also enhanced the transient response of the proposed OCL-LDO. To substantiate the proposed DAFFC, a telescopic cascode output stage for error amplifier, and two on-chip compensation capacitors (5 and 1 pF, respectively) are needed. The proposed OCL-LDO has been implemented in 65-nm CMOS technology and the active chip area is 0.0105 mm2. The output voltage is 0.8 V, and the minimum input voltage is 0.95 V at 100-mA loading current. The proposed OCL-LDO can work stably in a load range of 0 to 100 mA with 14-μA quiescent current. [ABSTRACT FROM AUTHOR]

The flipped-voltage-follower-based low-dropout regulator (LDO) has drawn attention for its fast response and reduced complexity, while super source follower can be combined to push the pole at the gate of the pass device to high frequency. But the maximum load current and minimum load capacitance of this topology are limited, especially when the poles and zero from the SSF are omitted in previous designs. This paper proposes a solution to extend the ranges of the load current and load capacitance, by implementing a small feed-forward capacitor ($C_{F}$) and a damping factor control circuitry. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot. The proposed LDO is verified in a 65-nm CMOS process with 0.008 mm2 active area. The measured voltage undershoot is 80 mV with a load steps from 100 μA to 50 mA with 2-ns edge times, with no external capacitor. And the maximum load capacitance can be extended to 2 nF. A figure-of-merit of 0.8 mV is achieved. [ABSTRACT FROM AUTHOR]

In this paper, we explore the challenges of implementing resonant converters using silicon carbide (SiC) power devices at high frequency: namely, the issue of high parasitic inductance packages and the ability to drive and enhance the mosfet at these frequencies. Although power circuit designers have many alternative device technologies to choose from, such as silicon and gallium nitride materials, SiC devices have several advantageous attributes especially in high power applications. As a solution, we study the device performance and parasitics of SiC mosfets in different packaging schemes. We further offer a solution to the challenges of driving SiC devices by demonstrating a multiresonant gate driver and use this scheme to drive an SiC mosfet at 30 MHz and a SiC JFET at 13.56 MHz in a class-E inverter, achieving 85.7 $\%$ drain efficiency for the mosfet and 93.8 $\%$ for the JFET. [ABSTRACT FROM AUTHOR]

The right-half-plane (RHP) zero in a continuous conduction mode boost converter results in a significantly restricted closed-loop bandwidth (BW) for higher voltage gain and/or load current conditions. A compensating ramp is used for current-mode control (CMC), and a higher ramp slope degrades the BW. Variable-frequency digital CMC offers inherent current-loop stability and real-time tuning scope for higher closed-loop BW. However, the challenges are to select the sampling frequency and sampling instant of the output voltage with discontinuous ripple due to the effective series resistance of the output capacitor, and its impact on stability. This paper shows that an event-based current-mode constant off-time digital modulator achieves superior stability and performance in a boost converter along with the reduced RHP zero effect over other digital CMC techniques. Using a discrete-time framework, the fast-scale stability conditions and small-signal models are analytically derived for various digital CMC techniques, which are validated using SIMPLIS simulation. A boost converter prototype is tested, and the analytical predictions are verified experimentally. Further, the analysis is extended to a non-inverting buck–boost converter. [ABSTRACT FROM AUTHOR]

Owing to the high operation frequency and fast switching speed, gallium nitride (GaN) devices are prone to the false turn-on phenomenon, causing high switching loss, shoot through, and even sustained oscillation. However, most of research on false turn-on aims at the enhancement-mode GaN devices, whereas there is still little published research on GaN devices in cascode configuration due to the comparatively complicated structure and various parasitic components. This paper conducts a comprehensive and in-depth study for the problem of false turn-on in cascode GaN devices based half-bridge circuits, which has a great guiding significance in the device selection, printed circuit board (PCB) design, and debugging of cascode GaN converters. In this paper, a novel analytical model of the device suffering false turn-on is first developed, with all the parasitic parameters being fully considered. Based on the model, the quantitative and accurate expression of the induced gate-to-source voltage is derived, which can serve as a precise and significant reference for judging and evaluating the false turn-on problems. Then, the influences of device and circuit parameters on the peak value of induced voltage are first investigated in detail, providing a reliable guidance for the usage and PCB design of cascode GaN devices based half-bridge converters. What's more, guidelines to effectively suppress the false turn-on phenomenon are also given, which can be adopted both in the design and debugging process of cascode GaN applications. Finally, all the theoretical calculations and analysis are verified by experiments with satisfying results and performances. [ABSTRACT FROM AUTHOR]

Parasitic ringing is commonly observed during the high-speed switching of wide band-gap (WBG) devices. Additional loss contributed by parasitic ringing becomes a concern especially for high switching frequency applications. This paper investigates the effects of parasitic ringing on the switching loss of WBG devices in a phase-leg configuration. An analytical switching loss model considering parasitics in power devices and application circuit is derived. Two switching commutation modes, gate drive dominated mode and power loop dominated mode, are investigated, respectively, and the switching loss induced by damping ringing is identified. It is found that this portion of the loss is at most the energy stored in parasitics, which always exists regardless of the switching speed and parasitic ringing. Therefore, with the given WBG device in the specific application circuit, damping more severe parasitic ringing during faster switching transient would not introduce higher switching loss. Additionally, the extra switching loss induced by resonance among parasitics and crosstalk is investigated. It is observed that severe resonance and its resultant over-voltage during the turn-on transient worsen the crosstalk, causing large shoot-through current and excessive switching loss. The theoretical analysis has been verified by the double pulse test with a 1200-V/50-A SiC-based phase-leg power module. [ABSTRACT FROM AUTHOR]

The design of a self-driving RF-DC rectifier needs to synchronize the gate driving and RF power input. A waveform-based design method is proposed in this paper to get this synchronization through a direct network-parameter calculation of the coupling and matching circuit, other than introducing an adjustable phase shifter on its dual power amplifier prototype. In order to get a practical design at microwave band, nonlinear feedback capacitances, package parasitics, and device's I-V curves are considered in the large-signal RF-DC rectifier circuit analysis. The external passive matching network characterized by its Z-parameters can be determined in order to realize a specific high-efficiency operation mode, which is quantified by waveform distance. An RF-DC class-E rectifier example at 2.8 GHz is given to demonstrate this design method based on a modified GaN device model including negative drain voltages. Rectification efficiency of 70.8% is measured for a 10 W input power at 2.8 GHz. [ABSTRACT FROM AUTHOR]