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Critical conduction mode (CRM) or discontinuous conduction mode (DCM) boost power factor correction (PFC) converter is widely used in low power applications for its advantages of zero-current turn-on of the switch, no reverse recovery in diode, and simple control. The input current of fixed switching frequency control CRM boost PFC converter and the input current of constant duty-cycle control DCM boost PFC converter mainly contain third harmonic. Moreover, the phase of the third harmonics is opposite. This article proposes a harmonic elimination parallel control to connect these two converters in parallel. The input current third harmonic of the parallel converter can be eliminated completely so as to improve the PF to nearly unity in the whole input voltage range. This parallel method is an interesting way to extend power, and is different from the existing method of parallel DCM boost PFC converter or parallel CRM boost PFC converter. The experimental results verify the accuracy of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This article proposes a unified pulsewidth-cycle (UPWC) control strategy to achieve mixed-mode operation and consistent valley switching (VS) for boost power factor correction converter. Compared with conventional single-mode controllers, it has a unified scheme to achieve single discontinuous conduction mode (DCM), single critical conduction mode (CRM), or mixed DCM/CRM operations in each half-line cycle. To regulate the input current as a sinusoid, the UPWC controller adopts a variable pulsewidth and a near-constant switching cycle under DCM, while adopts a constant pulsewidth and a variable switching cycle under CRM. To facilitate analysis, normalized mapping of operation modes is provided, along with the final pulsewidth and switching cycle. Furthermore, to ensure consistent VS, a controlled zero current detection method is proposed to fix the turn-on point of the power switch. No matter in DCM or CRM, consistent VS reduces both the switching loss and current distortion caused by parasitic resonance. To further reduce the current distortion caused by fixing the turn-on point, a compensation gain is provided that reshapes the input current as a sinusoid. Finally, through mixed DCM/CRM operation and consistent VS, the proposed UPWC controller achieves preferable performances in the power range, efficiency, power factor, and current distortion. [ABSTRACT FROM AUTHOR]

Maximizing the efficiency and power density of dc–dc converters demands parallel optimizations in design and control, especially for variable-frequency converters operating over wide frequency ranges. This letter presents the full-scale optimization of a kilowatt-range megahertz-class boost converter based on the impulse rectification. To maximize the heat extraction from the converter and increase its power density, the entire power stage is implemented on a single-layer insulated-metal substrate. For high efficiencies over wide frequency ranges, high-performance gallium nitride transistors are employed and various high-frequency materials (MnZn, NiZn, and air) with different geometries are compared to realize a wide-bandwidth inductor. Silicon carbide Schottky diodes with a zero reverse recovery are utilized for efficient high-frequency rectification, and the impact of the device's current rating on its generated reactive power and the overall system efficiency are investigated at different power levels up to 1 kW. The proposed optimum duty cycle control maximizes the conversion efficiency at different gains and powers and prevents fatal device hard switching at high frequencies. The optimized converter enables a peak efficiency of 98.6% along with an ultrahigh power density of 52 kW/l (850 W/in3). A loss breakdown summarizes major efficiency bottlenecks to be overcome by future advances in power electronics. [ABSTRACT FROM AUTHOR]

Utility power lines voltage levels vary in different geographical locations, ranging from 208 to 480 Vrms. Power factor correction (PFC) converters are typically designed for a particular input voltage and do not accept a wide range of line voltages. This results in multiple product designs and revisions and increased production costs to accommodate the various ac voltage levels used around the world. A PFC converter capable of coping with a wide input voltage range, from 90 Vrms up to 530 Vrms, would significantly decrease costs and streamline development. In this article, an extended input voltage range PFC converter is proposed, which provides a high and almost flat efficiency curve throughout the entire operating voltage range with an 800 VDC bus voltage. The proposed converter has a flexible bridgeless structure with simple control, low-current ripples, low common mode noise, and startup inrush current handling capabilities. Theoretical analysis and waveforms are discussed and experimental results for a 2-kW prototype are given, thereby validating the expected behavior. The operation of the proposed extended input voltage range PFC converter is also compared to the traditional totem-pole PFC showing more than 1% efficiency improvements at full load and a higher power factor in the proposed design. [ABSTRACT FROM AUTHOR]

The discontinuous conduction mode boost power factor correction converter features zero-current turn-on for the switch, no reverse recovery in diode, and constant frequency operation. With traditional constant duty ratio control, the power transfer in each switching cycle exhibits great difference during a half-line cycle. Consequently, the peak and root mean square values of the inductor current are large, the same goes for the switch and diode. This increases not only the current stress of the power components but also the conduction and switching turn-off loss, and lowers the efficiency of the converter. Introducing third and fifth harmonics into the input current and varying the duty cycle correspondingly can reduce the aforementioned power transfer difference, and provide huge space for the increment of boundary inductance as well. An optimum boundary inductance control concerning limited power factor (PF) is proposed in this paper. For the maximum boundary inductance of the converter within wide input voltage range, the optimum harmonics amounts are analyzed and figured out. The proposed method brings about efficiency improvement, output voltage ripple reduction, and PF increase as well, especially at high input voltages. A prototype has been built and the experimental results are presented to show the validity of the scheme. [ABSTRACT FROM AUTHOR]

Boost-based converters are used in a variety of non-isolated step-up applications, such as power factor correctors, because of their simplicity. The power density of these converters can be increased in higher switching frequencies, which reduces the size of the magnetic elements. This increases the switching losses, but that can be solved by soft-switching techniques. This paper proposes a resonant bridgeless power factor correction converter that provides soft switching for all of the semiconductors. The proposed structure can provide zero voltage switching for the switches and zero current switching for the diodes. In the proposed structure, the input current is inherently sinusoidal with low total harmonic distortion, even with small inductances. Therefore, a high input power factor is achieved without requiring a current control loop in the circuit. This reduces the complexity of the control circuit. An experimental prototype has been constructed to investigate the validity of the claims. Experimental results show near-unity power factor, as well as $\text{2}\%$ efficiency improvement at full load when compared to a conventional interleaved boost converter with the same components. [ABSTRACT FROM AUTHOR]

Digital peak current mode (DPCM) control is widely used for dc–dc converters operating in continuous current mode. However, current tracking delay (CTD) in the system is normally neglected in the modeling stage, which leads to poor compensator design and degraded performance. This paper investigates CTD effect in boost converter with different DPCM controls. Based on dynamic relationship between the reference current and actual inductor current, the CTD transfer functions are derived, which improves the accuracy of small signal model. Since CTD degrades the phase margin of the system, equivalent migration of right half plane zero is proposed to model CTD effect. This method is very simple and straightforward, which facilitates the compensator design. Furthermore, two novel DPCM control strategies with minimized CTD are proposed, and they are based on duty cycle restriction and duty cycle extension, respectively. Both controls greatly reduce the CTD effect and improve the response speed. Besides, the duty cycle extension benefits from an extended pulsewidth modulation (ExPWM). This optimizes the calculation algorithm and speed, while improving the time margin for digital calculations. Combined with the proposed models and controls, the CTD effect is greatly reduced. The effectiveness is verified through detailed simulations and experiments. [ABSTRACT FROM AUTHOR]

In order to overcome the limitations of the existing classical and solid-state Marx pulse generators, this paper proposes a new modular multilevel voltage-boosting Marx pulse generator (BMPG). The proposed BMPG has hardware features that allow modularity, redundancy, and scalability as well as operational features that alleviate the need of series-connected switches and allows generation of a wide range of pulse waveforms. In the BMPG, a controllable, low-voltage input boost converter supplies, via directing/blocking (D/B) diodes, two arms of a series modular multilevel converter half-bridge sub-modules (HB-SMs). At start up, all the arm's SM capacitors are resonantly charged in parallel from 0 V, simultaneously via directing diodes, to a voltage in excess of the source voltage. After the first pulse delivery, the energy of the SM capacitors decreases due to the generated pulse. Then, for continuous operation without fully discharging the SM capacitors or having a large voltage droop as in the available Marx generators, the SM capacitors are continuously recharged in parallel, to the desired boosted voltage level. Because all SMs are parallelly connected, the boost converter duty ratio is controlled by a single voltage measurement at the output terminals of the boost converter. Due to the proposed SMs structure and the utilization of D/B diodes, each SM capacitor is effectively controlled individually without requiring a voltage sensor across each SM capacitor. Generation of the commonly used pulse waveforms in electroporation applications is possible, while assuring balanced capacitors, hence SM voltages. The proposed BMPG has several topological variations such as utilizing a buck–boost converter at the input stage and replacing the HB-SM with full-bridge SMs. The proposed BMPG topology is assessed by simulation and scaled-down proof-of-concept experimentation to explore its viability for electroporation applications. [ABSTRACT FROM AUTHOR]

This paper contains a comparison between three topologies of a three-phase two-level inverter: A quasi-Z-source inverter (qZSI), a voltage-source inverter with a boost converter and a voltage-source inverter with an interleaved boost converter. experimental results obtained from laboratory tests of equivalent 6-kW 100-kHz inverters based on SiC mosfets and Schottky diodes are provided. The following parameters are compared: Quality of input inductor current and output phase voltage as well as total power losses in the inverters. The results for these parameters are obtained for input voltage ranging from 325 V to almost 600 V (where feasible), for two sets of equivalent modulation methods (two regular methods and two reduced-loss methods), for a couple of characteristic values of deadtime and for the operation both at the maximum value of modulation index and at equal values of voltage across the inverter bridge. Results of the experiments show that the qZSI topology may, at certain conditions, surpass the traditional two-stage inverter topologies in the areas of input inductor current quality, output voltage quality and also power losses (at high values of input voltage). What is needed to obtain that is a careful examination of operating conditions, applied modulation method and deadtime value. [ABSTRACT FROM AUTHOR]

A family of dimmable ac light-emitting-diode (LED) drivers fed from dc voltages, is presented in this paper based on zero-current-switching quasi-resonant converters. The proposed family of drivers is based on replacing the diode in the conventional converter topologies (i.e., buck, boost, or buck–boost) by a string of high-brightness LEDs (HB-LEDs). Hence, the HB-LED string will be working as the rectifier diode and the load, switching at the same frequency of the main switch. In this case, the output current, which is experimentally validated, shows a negative current peak due to the reverse-recovery effect of the HB-LEDs. In order to reduce the reverse-recovery effect on the HB-LEDs, the main switch of the proposed topologies is replaced with a full-wave resonant switch, which makes possible to reduce the di/dt during the turn-off of the HB-LED string, therefore the reverse-recovery effect is eliminated. Moreover, the dimming of the HB-LEDs is done by means of changing the switching frequency of the converter by varying the turn-off, while keeping a constant turn-on time. The proposed converters are suggested to be used in a postregulator stage of an ac–dc converter or as the interface between the low-voltage bus and the HB-LED string in a dc nanogrid. In order to validate the analysis, the proposed topologies have been experimentally tested on a constructed prototype with an output power of 7.5 W, that is able to achieve an electrical efficiency of 94.5% and a luminous efficacy of 110 lm/W at full load. Moreover, the analysis has been extended to a comparison in terms of reliability with the conventional topologies on a 700-h test. [ABSTRACT FROM AUTHOR]

The main objective of this work is to provide an overview and evaluation of discrete model-predictive control (MPC)-based maximum power point tracking (MPPT) for photovoltaic systems. A large number of MPC-based MPPT methods have been recently introduced in the literature with very promising performance; however, an in-depth investigation and comparison of these methods has not been carried out yet. Therefore, this paper has set out to provide an in-depth analysis and evaluation of MPC-based MPPT methods applied to various common power converter topologies. The performance of MPC-based MPPT is directly linked with the converter topology, and it is also affected by the accurate determination of the converter parameters; sensitivity to converter parameter variations is also investigated. The static and dynamic performance of the trackers is assessed according to the EN 50530 standard, using detailed simulation models, and validated by experimental tests. The analysis in this work aims to present useful insight for practicing engineers and academic researchers when selecting the maximum power point tracker for their application. [ABSTRACT FROM AUTHOR]

This paper presents an integrated boost converter having very low output voltage ripple making it suitable for analog applications, which are sensitive to supply noise. Architecturally, the converter consists of a conventional boost converter followed by an L–C filter, which drastically reduces the output ripple. The L–C filter has been realized using 30-nH bondwire inductance and 0.54-nF on-chip capacitance. The converter switches at 118 MHz and produces a regulated 3.2-V output from an input voltage ranging from 1.0 to 2.7 V. The converter is able to deliver up to 65-mA current for input voltage $\geq$ 2.4 V. The prototype has been implemented in 0.18- $\mu$m standard digital CMOS process and the entire design consumes only 0.52-mm$^2$ chip area resulting in a maximum power density of 0.387 W/mm$^2$. Peak efficiency of the converter is 77.4% at 32.2-mA current for 2.7-V input supply. The measured maximum output ripple noise is 21 mV that is less than 0.65% of the regulated output voltage. [ABSTRACT FROM AUTHOR]

A starting and voltage spike suppression scheme is proposed and investigated in a three-phase isolated full-bridge boost power factor correction (PFC) converter with the passive flyback auxiliary circuit. In steady state, the auxiliary circuit in the PFC converter is operating as a passive clamp circuit, by which the voltage spike across primary side of the power transformer is suppressed, and the absorbed energy can be transferred to the load during one charging period by the resonance of the inductors and capacitors in the auxiliary circuit. In starting state, the output filter capacitor is charged by the flyback inductor in the auxiliary circuit, and the PFC converter can achieve normal starting-up. The operational processes of the PFC converter are analyzed in both steady and starting states. Furthermore, the design considerations of the key parameters are discussed. Finally, experimental study has been done on a laboratory-made three-phase PFC prototype, and the feasibility of the proposed scheme and the validity of the theoretical analysis are verified by the experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a novel ac/dc converter is proposed for low-voltage and low-power ac rectification applications. The proposed converter manages the energy harvested from microscale electromagnetic generators (MEGs). It integrates the conventional boost and buck–boost topologies with a shared inductor, a bidirectional switch, and two split filtering capacitors. The boost and the buck–boost topologies function in the positive and negative half input cycles, respectively. The inductor is energized by being shorted with the input source through the mosfet channel without using the diodes. This enables active rectification of low-amplitude (below 0.7 V) ac voltages. Theoretical analysis, design considerations, and control method are detailed. A 40-mW circuit prototype, which converts a 0.4-V peak, 100-Hz ac voltage source to 3.3-V dc, is designed and tested to verify the proof of concept. [ABSTRACT FROM AUTHOR]

A high-efficiency boost dc-dc converter with adaptive peak-inductor-current (APIC) control method is proposed. Besides, a novel two-step startup procedure is also proposed and applied on the boost converter. The proposed integrated boost converter was fabricated by using a 0.18-μm 1P6M mixed-signal process with a die area of 0.96 mm × 0.75 mm, and it is meant to be used with low-power, low-voltage green energy sources and batteries, such as fuel cells, solar cells, and nickel-metal hydride batteries. Hence, the power efficiency, minimal startup voltage, and minimal input voltage are the most important design considerations. The output voltage of the proposed converter is set to 1.8V, and the measured power efficiency is up to 90.6%, occurring when the input voltage is 1.3 V, the output voltage is 1.8 V, and the load current is 50 mA. According to the measured results, the proposed converter can start up successfully with a 0.43-V input voltage. Then, the input voltage can be further lowered to 0.22 V after startup. Moreover, both the efficiency and the output voltage ripple are improved with the proposed APIC method. Furthermore, a two-step startup procedure, which does not require any extra startup assist circuit, is proposed. [ABSTRACT FROM AUTHOR]

In this paper, the efficiency and power factor performance of improved power factor correction (PFC) topologies suitable for a high density and efficient design are compared. Several topologies, including a conventional average current mode control boost PFC, an interleaved boost PFC, a back-to-back bridgeless boost PFC, and a semi-bridgeless boost PFC, are assessed through loss analysis and simulation using whole height 1 U and 2 kW class prototypes. Based on this, an optimal topology is selected for which an additional comparative analysis involving input line measure improvement control is conducted. The results of these experiments can be adapted for use in the circuit selection of high-performance converters with power factor improvement circuits. [ABSTRACT FROM AUTHOR]

An effective way of reducing differential mode (dm) noise of switching converters is still an open issue. Here, a thorough investigation of the filtering technique with integrated magnetics, taking nonideal effects into account is presented. Parasitic components and component variations due to tolerances are considered, and the obtainable attenuation is calculated. This paper also gives an analysis of the optimized coupling factor, as well as the distribution of the capacitance between the two capacitors involved. The entire analysis is done in the frequency domain. Therefore, a proper model is given. In order to show the relevance of this paper, a practical validation is presented. Finally, a dm noise comparison between the regular boost converter and the boost converter with an incorporated smoothing transformer in a real hardware prototype for the input stage of a laptop adapter shows the dm filtering effectiveness of the smoothing transformer. [ABSTRACT FROM AUTHOR]

The second part of the essence of three-phase PFC Rectifier Systems is dedicated to a comparative evaluation of four active three-phase PFC rectifiers that are of interest for industrial application: the active six-switch boost-type PFC rectifier, the Vienna Rectifier (VR), the active six-switch buck-type PFC rectifier, and the Swiss Rectifier. Typical dynamic feed-back control structures of the considered topologies are shown, and analytical equations for calculating the current stresses of the power semiconductors are provided. In addition, EMI filtering is discussed. The rectifier systems are assessed and compared based on simple and demonstrative performance indices such as the semiconductor stresses, the required semiconductor chip area, the volume of the main passive components, the DM and CM conducted EMI noise levels, and the efficiency. Two implementation variants, a more advanced one using SiC JFETs and SiC Schottky diodes and one using Si IGBTs and SiC Schottky diodes, are considered. The comparison is extended with selected examples of hardware demonstrators of VR systems that are optimized for efficiency and/or power density. This allows to determine the tradeoff between efficiency and power density and to quantify a typical efficiency versus power density limit (Pareto-Front) for practical three-phase PFC rectifier systems using standard printed circuit board interconnection technology. [ABSTRACT FROM AUTHOR]

In this paper, a single-stage ac–dc power electronic converter is proposed to efficiently manage the energy harvested from electromagnetic microscale and mesoscale generators with low-voltage outputs. The proposed topology combines a boost converter and a buck-boost converter to condition the positive and negative half portions of the input ac voltage, respectively. Only one inductor and capacitor are used in both circuitries to reduce the size of the converter. A 2 cm × 2 cm, 3.34-g prototype has been designed and tested at 50-kHz switching frequency, which demonstrate 71% efficiency at 54.5 mW. The input ac voltage with 0.4-V amplitude is rectified and stepped up to 3.3-V dc. Detailed design guidelines are provided with the purpose of minimizing the size, weight, and power losses. The theoretical analyses are validated by the experiment results. [ABSTRACT FROM AUTHOR]

This paper introduces the design of integrated BiCMOS current-sensing circuit and amplifier for high-performance current-mode dc-dc boost converter. By exploiting the advantage presented by the integration of both CMOS and bipolar devices within same technology, the BiCMOS circuits offers high-gain amplifier and accurately sensed inductor current. The error amplifier has BJT differential pair and current sources to obtain a fast response, while the current-sensing circuit exploits a current-mirror instead of opamplifier as a voltage follower. The test in 0.35-μm BiCMOS process shows that the transient time of the error amplifier is about 4 μs and the current-sensing circuit can operate with accuracy of 88% at the frequency of 20 kHz. The output voltage of 4.8-8 V is obtained at the input voltage of 3-5 V with the ripple ratio within 5%. [ABSTRACT FROM AUTHOR]

An advanced symmetrical voltage quadrupler rectifier (SVQR) is derived in this paper to serve as the secondary rectification topology, which helps to extend the converter voltage gain and reduce the output diode voltage stresses. The output voltage is four times of the conventional full-bridge voltage rectifier with the same transformer ratio, which benefits to reduce the turns ratio of the transformer and decrease the parasitic parameters. Also, low voltage-rated diodes with high switching performance can be applied to improve the efficiency. Meanwhile, all the diodes in SVQR have the same voltage and current stresses, which simplifies the thermal design. Furthermore, two output electrolytic capacitors are connected in series to share the high output voltage, and the voltage balance can be realized naturally without any additional voltage-sharing scheme. A clear picture is made in this paper to give a general framework and universal applications for the derived SVQRs for high step-up and high output voltage conversion systems. A dual boost converter is used as an example to demonstrate the clear advantages of the derived SVQRs. [ABSTRACT FROM AUTHOR]

In the first part of this paper, three-phase power factor correction (PFC) rectifier topologies with sinusoidal input currents and controlled output voltage are derived from known single-phase PFC rectifier systems and/or passive three-phase diode rectifiers. The systems are classified into hybrid and fully active pulsewidth modulation boost-type or buck-type rectifiers, and their functionality and basic control concepts are briefly described. This facilitates the understanding of the operating principle of three-phase PFC rectifiers starting from single-phase systems, and organizes and completes the knowledge base with a new hybrid three-phase buck-type PFC rectifier topology denominated as Swiss Rectifier. Finally, core topics of future research on three-phase PFC rectifier systems are discussed, such as the analysis of novel hybrid buck-type PFC rectifier topologies, the direct input current control of buck-type systems, and the multi-objective optimization of PFC rectifier systems. The second part of this paper is dedicated to a comparative evaluation of four rectifier systems offering a high potential for industrial applications based on simple and demonstrative performance metrics concerning the semiconductor stresses, the loading and volume of the main passive components, the differential mode and common mode electromagnetic interference noise level, and ultimately the achievable converter efficiency and power density. The results are substantiated with selected examples of hardware prototypes that are optimized for efficiency and/or power density. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase power factor corrector based on a tapped-inductor buck–boost converter. This paper suggests simplified models of the power stage under current-mode control and derives small-signal transfer functions of both the current and voltage control loops. Design rules for implementation of the proposed power factor corrector (PFC) are also suggested. The proposed PFC features low dc bus voltage, arbitrary lower than the peak line voltage. The proposed PFC is suitable for applications in computers and communications, where dc isolation can be provided by the downstream dc/dc converters. Simulation and experimental results are also reported and stand in good agreement with theoretical expectations. [ABSTRACT FROM AUTHOR]

The effects of switching asymmetry and flux walking on an isolated current-fed full-bridge boost converter are presented with two different secondary configurations: a voltage doubler (VD) and a diode bridge (DB). The results show that a drop in the converter efficiency is clearly visible when there are switching asymmetries in the DB configuration, whereas the VD configuration is more tolerant of switching asymmetries because of its inherent capability to oppose flux walking. [ABSTRACT FROM AUTHOR]

This paper presents a new wide-input-wide-output dc-dc converter, which is an integration of buck and boost converters via a tapped inductor. Coherent transition between step-down and step-up modes is achieved by a proper control scheme. This paper presents theoretical concepts and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a two-phase interleaved critical mode (CRM) power factor correction (PFC) boost converter with a novel closed loop interleaving technique. This new interleaving technique makes each phase work at ideally CRM. Natural current sharing and precise 1800 phase shift are achieved. The scheme can be easily integrated into a PFC control chip. Full-order averaged model of CRM boost is derived to analyze the stability of the converter. The loop response and stability of the closed-phase regulation loop have been analyzed. A 400W two-phase interleaved CRM PFC boost converter prototype is built. This proposed scheme is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

A new zero voltage switching (ZVS) boost converter is presented in this paper. By using an auxiliary switch and a capacitor, ZVS for all switches is achieved with an auxiliary winding in one magnetic core. A small diode is added to eliminate the voltage ringing across the main rectifier diode. This clamping technique can also be utilized in other dc-dc converters, and a family of new ZVS dc-dc converter is derived. A prototype (500 W/193 kHz) is made to verify the theoretical analysis. The efficiency is higher than 94% at 90-V input at full load. [ABSTRACT FROM AUTHOR]

This paper presents an approach to continuous variable design optimization of a power electronics converter. The objective of the optimization approach is to minimize the total component cost. The methodology is illustrated with the design of a boost power factor correction front-end converter with an input electro- magnetic interference filter. The system design variables are first identified. The relevant system responses and component costs are then expressed as a function of these design variables. Finally, by using mathematical optimization techniques, the design variable values that minimize the total system component cost are obtained, given practical constraints on these design variables and system responses. [ABSTRACT FROM AUTHOR]