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High junction temperature is usually the main factor leading to device failures in high-power working conditions, such as surges or avalanches. It is of great significance to obtain the junction temperature quickly and accurately. Direct measurement of junction temperature is inconvenient, and usually indirect electrical measurement combined with model calculation is used. An electrothermal coupling junction temperature calculation model with distributed heat sources is proposed in this article. This model can accurately and quickly predict the device behavior during the surge process, as well as the voltage drop and temperature changes of each part of the device, without actually performing surge tests. This article describes the theoretical basis and calculation principles of the model. By taking a commercial SiC merged PiN Schottky diode as an example, this article also explains the details of the establishment of the electrical and thermal characteristic models of the device, as well as the calculation steps of the junction temperature by the thermal coupling model. The calculated device voltage drop curve of the device is in good agreement with the measured ones, and the calculated junction temperature curve is more consistent with the device failure mechanism than the one by the traditional RC thermal circuit model. [ABSTRACT FROM AUTHOR]

The hybrid switch (HyS) configured by paralleling silicon Si-IGBT and silicon carbide SiC-mosfet mosfet (SiC/Si HyS) has been widely investigated because of high efficiency as well as low cost. However, one of the main obstacles in the practical application of HyS is the complicated gate driver circuits. Generally, one HyS requires two driver chips and two driving signals to achieve flexible triggering patterns, which leads to more cost and more control complexity. To solve the problems, in this article, a compact gate driver circuit with one driver chip and one driving signal is proposed for HyS working in all commonly used triggering patterns. The operation principle, mathematical analysis of time delay, maximum switching frequency, and the relationship between delay time and triggering pattern are investigated in detail. The modeling and systematical analysis of the turning off transient process are given to clarify the current overshoot generation mechanism for the first time, which is helpful for the designer to consider the device ratio for the reliable operation of HyS. The merits of the proposed driver circuits are simple structure, low control complexity, and low cost, more importantly, providing more flexibility for realizing the commonly used triggering patterns. The feasibility and effectiveness of the proposed HyS gate driver circuit are evaluated by a 2-kW SiC/Si HyS Buck converter prototype with triggering patterns C, D, E, and F. The gate driver circuit with variable triggering patterns design guideline is outlined in this article, which helps the enterprise to integrate a new generation of driver circuit for HyS to facilitate the application of HyS as three terminals devices. [ABSTRACT FROM AUTHOR]

An analysis of the transient behavior of dc networks consisting of voltage sources, capacitors, and series loss-free resistors (SLFRs) is presented. The realization of an SLFR was achieved by means of a topological variation of the positive output voltage buck–boost converter operated in discontinuous-conduction mode. It is demonstrated that even simple RC circuits containing SLFRs exhibit behavior that is described by Abel nonlinear differential equations, which do not have an exact analytical solution. Some possible applications of the SLFRs in power electronics, dc microgrids, and renewable energy power systems include loss-free charge and discharge of capacitor banks, voltage equalization of capacitors, and loss-free voltage clamping circuits. The concept of the SLFR can also be applied for voltage control in dc microgrids, employing the droop voltage technique, equalization of power and current in voltage sources associated in parallel (including batteries and dc–dc converters), and also input and output voltage natural balance in input-series output-series association of dc converters. The theoretical analysis results are validated via numerical examples and computer simulation. [ABSTRACT FROM AUTHOR]

Hybrid switches are attracting increasing attention recently, due to their high efficiency and low cost. Normally, two separated gate drivers and driving signals are needed for the hybrid switch, which leads to more cost and more control complexity. A novel gate driver circuit for SiC+Si hybrid switches is proposed using single driving signal and single-gate driver in this article. Two simple resistance-capacitance (RC) delay circuits are used for generating different time-delays required by two different triggering patterns to provide more flexibility. The detailed operation principles, mathematical analysis, and the guidance for the selection of key components of the proposed circuit are provided. The merits of the proposed driver are: first, simple structure; second, low control complexity; third, more flexibility; and fourth, low cost. A 2-kW Silicon Carbide (SiC)-MOSFET+Si-insulated gate bipolar transistor (IGBT) hybrid switch buck converter is built to validate the proposed gate driver circuit. The analysis and experimental results match very well, which shows the effectiveness and merits of the proposed method. [ABSTRACT FROM AUTHOR]

This letter proposes a new submodule capacitor condition monitoring method for modular multilevel converters (MMCs) based on the dc-side start-up procedure. During this process, the MMC can be simplified into an RC charging circuit, and the submodule capacitance can be estimated by investigating its relationship with the phase current and submodule voltage. Several practical issues related to the implementation, advantages, and limitations of the proposed method are presented as well. In order to validate the method, a series of experiments with different submodule capacitances are conducted based on a three-phase MMC platform. Experimental results confirm the effectiveness and feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

Wide bandgap devices such as gallium nitride (GaN) devices are being widely used due to their low on-resistance and parasitic parameters that can improve system performance compared to Si mosfets. However, these advantages mentioned above can sometimes lead to unexpected behavior in practical systems, such as false triggering oscillation. False triggering oscillation may cause overshoot, electromagnetic interference, shoot-through, and even device damage, which seriously affects the performance of the system. In this paper, an RC snubber circuit is proposed to suppress false triggering oscillation in a half-bridge circuit, and the design method of the RC parameters is proposed. The proposed oscillation suppression method is simpler, easier to implement, and more effective than the active gate driver. In addition, it can provide guidance for oscillation suppression design in high-order systems. First, the double pulse circuit is used as an example to analyze false triggering oscillation and its high-frequency equivalent circuit is obtained. Then, the RC region is established by scrutinizing the characteristic equations via a root locus method. The RC snubber circuit has better oscillation suppression effect when the RC parameters are within the region rather than outside the region. Finally, the RC region designed by the proposed method is verified by simulation and experiment results, and the proposed method indicates a substantial improvement of the switching characteristics of the controlled device at turn-off. [ABSTRACT FROM AUTHOR]

The efficiency and output power of a high- $Q$ Class-E power amplifier (PA) are very sensitive to the values of the circuit components. Any mismatch between the nominal Class-E frequency and the input clock frequency could result in considerable degradation in the efficiency and much change in the output power. In this paper, we present a new self-oscillating Class-E PA, or so-called Class-E power oscillator (PO), whose feedback network is mainly constructed of a low- $Q$ RC circuit. As a result, the phase response of the feedback network is almost flat around the operating frequency, and if the nominal Class-E frequency of the load network changes due to variations in the component values, the phase shift in the feedback network does not change considerably, and therefore, the Class-E operation of the circuit is substantially maintained. We also present a complete design procedure for the proposed Class-E PO. We have built and tested a sample Class-E PO based on the proposed circuit. At $V_{DD}= {\text{4.5}}\,{\text{V}}$ , the measured oscillation frequency, output power, and efficiency of the circuit are 800 kHz, 0.96 W, and 89%, respectively. Simulation and measurement results confirmed that the efficiency and output power of the proposed Class-E PO have small sensitivities to the variations in the component values; therefore, we call the proposed circuit a self-tuned Class-E PO. [ABSTRACT FROM AUTHOR]

This paper is concerned with the thermal models which can physically reflect the heat-flow paths in a lightweight three-phase half-bridge two-level SiC power module with six MOSFETs and can be used for coupled electrothermal simulation. The finite-element (FE) model was first evaluated and calibrated to provide the raw data for establishing the physical resistor–capacitor (RC) network model. It was experimentally verified that the cooling condition of the module mounted on a water cooler can be satisfactorily described by assuming the water cooler as a heat exchange boundary in the FE model. The compact RC network consisting of 115 R and C parameters to predict the transient junction temperatures of the six MOSFETS was constructed, where cross-heating effects between the MOSFETs are represented with lateral thermal resistors. A three-step curve fitting method was especially developed to overcome the challenge for extracting the R and C values of the RC network from the selected FE simulation results. The established compact RC network model can physically be correlated with the structure and heat-flow paths in the power module, and was evaluated using the FE simulation results from the power module under realistic switching conditions. It was also integrated into the LTspice model to perform the coupled electrothermal simulation to predict the power losses and junction temperatures of the six MOSFETs under switching frequencies from 5 to 100 kHz which demonstrate the good electrothermal performance of the designed power module. [ABSTRACT FROM PUBLISHER]

Compared with single-module applications, unbalanced stray parameters come about frequently in the process of installing paralleled IGBT modules, which could result in some distinctions of current sharing and temperature distributions. To focusing on depicting this practical issue, a novel dynamic electrothermal model extended to paralleled systems is proposed in this paper to establish a comprehensive transient model to characterize the relations of power losses, junction temperature, and unbalanced parasitic elements. The model can describe the interactions of current distributions and thermal dissipations between paralleled modules. In addition, the variation of unbalanced temperature during transient process can be obtained with the proposed electrothermal model. First, the stray inductance parameters in the paralleled branches are analyzed in detail by finite-element-method simulation tool. And based on impedance analysis, an improved power loss model is built up, considering the interaction of paralleled devices. Moreover, by the method of resistor–capacitor networks extracted from numerical simulations of 3-D structural model, the transient thermal impedance of devices and cooling system is obtained for fast and accurate electrothermal cosimulation of the paralleled system. Experimental results are carried out to verify the proposed model and coincide with the theoretical analysis. [ABSTRACT FROM AUTHOR]

Obvious differences are observed between simulation and experimental results for series-connected insulated-gate bipolar transistors (IGBTs) using current IGBT models. Here, the cause of these errors is analyzed in detail. A physical model based on more effective assumptions for a 2-D structure is proposed in this paper. The relationship between carrier concentration and lifetime is considered in the model in order to achieve an accurate description for excess carrier distribution. Testing was performed in a buck converter using series-connected non-punch-through (NPT) planar-gate 6500 V/600 A high-voltage IGBTs (HVIGBTs) at various bus voltages using an asynchronous control signal. The accuracy of HVIGBT transient model is verified by comparing experimental and simulation results in buck converters using two and three series-connected IGBTs. The function of the RC snubber circuit is also evaluated using the proposed model. [ABSTRACT FROM AUTHOR]

A hardware efficient method and system for estimating the time constant and measuring the current of the output capacitors in digitally controlled switch-mode power supplies is introduced. The estimator emulates the equivalent RC circuit of the output capacitor with a much smaller version, placed in parallel, and adjusts its own resistance until the two circuits have the same time constant. The adjustment is based on a novel zero voltage crossing detection method and on synchronization with the digital pulse-width modulator operation. The effectiveness of the new estimator is verified with a 5 V to 1 V/5 A, 500-kHz buck converter prototype utilizing an optimal response controller. The experimental results show accuracy within a few tens of nanoseconds in the detection of capacitor zero-current crossing points, corresponding to a smaller than a 1.5% error in the time constant estimation, and, compared to an imperfectly tuned system, about 40% smaller voltage deviation during transients. [ABSTRACT FROM AUTHOR]

A new method to reduce common-mode (CM) electromagnetic interference (EMI) emission at the dc input of variable-speed motor drives is presented. Unlike conventional passive or active filtering techniques that rely on impedance mismatch or active noise cancellation, the proposed method uses a passive circuit with matched impedance to cancel the inverter CM current. In the proposed approach, a star-connected three-phase RC circuit is placed at the output of the inverter to extract the CM voltage. An inductor is connected between the star point of the RC circuit and the middle of the dc bus capacitor to inject a CM current into the dc input. A Wheatstone bridge is then identified in the CM equivalent circuit of the system with these additional components. By properly selecting the inductor, the Wheatstone bridge can be balanced, resulting in near-ideal cancellation of the input CM current. Development of the method is presented and an experimental setup is used to demonstrate its effects. A comparison with conventional EMI filtering methods in terms of overall filter volume is also presented. [ABSTRACT FROM AUTHOR]