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Gate-oxide degradation has been one of the major reliability challenges of SiC MOSFETs and should be monitored carefully to avoid unexpected power converter failures. Various precursors have been introduced in the literature for gate-oxide degradation monitoring. However, those proposed precursors are temperature dependent and it is highly challenging to eliminate temperature effects. In this article, two new temperature-independent precursors (Miller capacitance and gate–source capacitance changes) are proposed for gate-oxide degradation monitoring of SiC MOSFETs. During the accelerated aging tests under high electric field and high temperature, a consistent change in Miller capacitance and gate–source capacitance is reported for both common source and Kelvin source SiC MOSFETs. Also, the temperature sensitivity of each precursor is investigated. The proposed precursors enable the monitoring of gate-oxide degradation without decoupling the impact of package degradation. Based on the findings, a simple early warning in situ circuit is proposed to monitor gate-oxide aging. A comprehensive precursor comparison is provided to show the merits of the proposed precursors. Finally, the experimental results are presented to validate the efficacy of the in situ monitoring circuit. [ABSTRACT FROM AUTHOR]

Online junction temperature (Tj) measurement enables robust power converter operations by providing overtemperature protection and condition monitoring of the power devices. For SiC MOSFETs, the real-time (Tj) information is especially critical as limited field data are available regarding the reliability. In this article, utilizing the turn-on delay time as temperature sensitive electrical parameter, an online (Tj) measurement is realized through an intelligent gate drive. Specifically, the turn-on delay time is translated into the pulsewidth of a digital signal through the conditioning/logic circuits. During (Tj) measurements, the adjustable gate resistance circuit is activated to improve the measurement sensitivity beyond 600 ps/°C. Using the high-resolution capture module (300-ps resolution) in the system microcontroller, this pulsewidth is measured and then converted to junction temperature with a resolution of <0.5 °C. A prototype is built to validate the online (Tj) measurement method. The switching test results show that the circuit is able to precisely measure Td,on and offers a good linearity/sensitivity for (Tj) estimation. In the continuous operation, the junction temperature of a decapsulated device using an infrared camera and (Tj) obtained from the circuit match well with <1 °C difference under various operating conditions. In addition, the gate-oxide degradation's impact on Td,on is considered for SiC MOSFETs, and an aging compensation scheme is discussed to maintain the measurement accuracy throughout the device's lifetime. It is shown that the proposed circuit provides an accurate real-time (Tj) measurement for SiC MOSFETs, which can be deployed to improve the power converters’ reliability. [ABSTRACT FROM AUTHOR]

The temperature-sensitive electrical parameters (TSEPs) have been used in silicon carbide (SiC) mosfets junction temperature measurement for over-temperature protection and condition monitoring. However, the device aging can affect the TSEPs and thus leads to false ${\boldsymbol{T}}_{\boldsymbol{j}}$ measurement. In this article, the aging's impacts on various TSEPs are comprehensively investigated. Specifically, utilizing the dc power cycling test, both the gate oxide instability and package degradation are considered. Then the commercial devices with different structures are aged, and their temperature-dependent static and switching characteristics are evaluated at different aging cycles. Both the positive gate bias-induced threshold voltage shift and package degradation are observed, and their impacts on each TSEP are evaluated independently. Based on the evaluation results at various operating conditions, the temperature measurement errors due to different aging mechanisms are well summarized for each TSEP. From the dc power cycling test result, the package degradation's impact on TSEPs is found to be more significant than the gate oxide instability. It is pointed out that the aging's effect on TSEPs is an important factor that needs to be considered for accurate ${\boldsymbol{T}}_{\boldsymbol{j}}$ measurement in SiC mosfets. [ABSTRACT FROM AUTHOR]

When the interleaved boost power-factor correction (PFC) converter operates in a light load (<15% of nominal load), the phase-shedding control is commonly used to increase the converter's efficiency. If the inductors are coupled for high power density applications, because of the strong mutual effects of the coupled inductor, the switching of the operation phase may lead to a current flowing in the non-operation phase. In this paper, a two-phase interleaved boost PFC converter with a coupled inductor in the single-phase operation was analyzed. The operation modes of the converter in a switching cycle and a half line cycle were presented, and the modes’ variation with the load changes, as well as the power distribution, was provided. A 1-kW prototype was built to verify the analysis, and it was shown that the non-operation phase also delivers some power, which may worsen the converter's efficiency and distort the average input current waveform. [ABSTRACT FROM AUTHOR]

The dynamic on-resistance in gallium nitride (GaN) devices is problematic as it can impair the converter's efficiency due to the increased conduction loss. In this paper, the hard-switching transient's effect on the dynamic on-resistance is, for the first time, evaluated experimentally on a commercial high-voltage GaN high electron mobility transistor. A new ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ measurement circuit with fast sensing speed is designed, and an accurate measurement of ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ can be realized experimentally within 49.6 ns after the device's current reaches to the load current. A double-pulse-test setup is designed to comprehensively evaluate the switching transient's effect on ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ under different operating conditions. From the experimental results, it is found that the turn-on and turn-off gate resistance have a significant impact on the dynamic on-resistance whereas the cross-talk effect on ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ is negligible. Specifically, at 400 V/25 A, more than 27% (28.2%) increase in ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ is observed when the external turn-on (turn-off) gate resistance increases from 0 to 20 Ω. Detailed discussion and quantitative analysis are provided to explain the experimental results. In terms of the turn-on process, it is concluded that the ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ variation is mainly caused by the different numbers of generated hot electrons. For the turn-off transient, it is confirmed the variation of drain current at different dv/dt slew rate leads to the ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ difference. [ABSTRACT FROM AUTHOR]

Middle-point inductance ${{\boldsymbol L}_{{\boldsymbol {\text{middle}}}}}$ can be introduced in multiple-chip power module package designs. In this paper, the effect of middle-point inductance on switching transients is analyzed first using a frequency-domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying ${{\boldsymbol L}_{{\boldsymbol {\text{middle}}}}}$ , and extensive switching tests are conducted to evaluate the middle-point inductance's impact. Experiment result shows that the active mosfet's turn-on loss decreases at higher values of ${{\boldsymbol L}_{{\boldsymbol {\text{middle}}}}}$ , while its turn-off loss increases. Detailed analysis of this loss variation is presented. In addition to the switching loss variation, it is also observed that different peak voltage stresses are imposed on the active switch and antiparallel diode during the switching transients. Specifically, in the case of lower mosfet's turn-off, the maximum voltage of the lower mosfet increases as ${{\boldsymbol L}_{{\boldsymbol {\text{middle}}}}}$ goes up; however, the peak voltage of the antiparallel diode decreases significantly. The induced voltage spikes during upper mosfet turn-on process is also evaluated, and an opposite trend is observed experimentally. Analysis of the voltage overshoot variation is discussed. Based on the experimental evaluation and analysis, a multiple-chip power module package design guideline is summarized considering the middle-point inductance's effect. [ABSTRACT FROM AUTHOR]

A two-phase interleaved boost dc–dc converter with an inversely coupled inductor in a discontinuous-current mode (DCM) is analyzed by the equivalent inductance method. Coupling effects on the circuit statuses are described, and a forced conduction of the power diode or reverse-paralleled diode of MOSFET is caused by coupling. As a result, three major circuit statuses are figured out according to the physical relationship between the input–output voltage ratio and the coupling coefficient, and their condition boundaries are used to classify the DCM operation modes. Then, considering the load (duty cycle) variation, ten DCM operation modes are comprehensively analyzed. The analysis can be used to make an easy prediction of operation modes, and extended to the analysis of an interleaved buck converter or buck/boost bidirectional converter with a coupled inductor in DCM. At last, a 300-W prototype is built and tested in the lab to verify the analysis. [ABSTRACT FROM PUBLISHER]

With the increased cloud computing and digital information storage, the energy requirement of data centers keeps increasing. A high-voltage point of load (HV POL) with an input series output parallel structure is proposed to convert 400 to 1 VDC within a single stage to increase the power conversion efficiency. The symmetrical controlled half-bridge current doubler is selected as the converter topology in the HV POL. A load-dependent soft-switching method has been proposed with an auxiliary circuit that includes inductor, diode, and MOSFETs so that the hard-switching issue of typical symmetrical controlled half-bridge converters is resolved. The operation principles of the proposed soft-switching half-bridge current doubler have been analyzed in detail. Then, the necessity of adjusting the timing with the loading in the proposed method is analyzed based on losses, and a controller is designed to realize the load-dependent operation. A lossless RCD current sensing method is used to sense the output inductor current value in the proposed load-dependent operation. Experimental efficiency of a hardware prototype is provided to show that the proposed method can increase the converter's efficiency in both heavy- and light-load conditions. [ABSTRACT FROM AUTHOR]

In this paper, the differential-mode (DM) electromagnetic interference (EMI) noise of a single-phase boost power factor correction converter operating in critical current mode was analyzed. The DM noise spectra are calculated based on the mathematical model of EMI receiver and the required corner frequencies of DM filter are obtained. It can be seen that the minimum corner frequencies are determined by the maximum noises at 150 kHz. With the relation between the magnitude of the inductor current ripple and the DM noise, the characteristics of noise at 150 kHz are obtained by analyzing the current ripple magnitude at 150 kHz; thus, the worst conditions which have the maximum noise value are figured out. Meanwhile, the maximum noises at 150 kHz for different input voltages are identical, so the DM filter can be designed based on one worst spectrum at one input voltage without testing the spectra in other conditions. [ABSTRACT FROM AUTHOR]

Interleaved critical current mode (CRM) boost power factor correction (PFC) converter is widely employed recently for its high power density. In order to further reduce the volume and the copper usage of the magnetic components, two-phase interleaved CRM boost PFC converter with a coupled inductor is analyzed in this paper. The coupling effects on the input current, the inductor current, the switching frequency and the flux linkage are analyzed separately. If the self-inductances and the magnetic core are the same for both coupled and noncoupled inductors, the number of winding turns of coupled inductor is fewer than that of the noncoupled inductor, which implies a lower cost. Although the input current ripple increases a little since coupling, a reduction in the total volume of magnetic components, including the electromagnetic interference filter and the coupled inductor, is possible if the coupling coefficient is made reasonable. [ABSTRACT FROM AUTHOR]

A buck power factor correction (PFC) converter is widely used in low-power applications for its high efficiency in the entire universal input voltage range. However, because of the inherent dead zone, the input power factor (PF) is not high. A buck PFC converter operating in a discontinuous conduction mode is introduced. When the duty cycle is constant during the line cycle, the input current contains a large amount of negative third harmonic, especially at a low input voltage. By proposing an optimum third harmonic injection during the nondead zone and its control implementation, a higher PF and a lower output voltage ripple within the entire universal input voltage range are achieved. The experimental verifications are carried out on a 120-W prototype with universal input. [ABSTRACT FROM PUBLISHER]

A three phase single switch boost rectifier, operating in a quasi-critical conduction mode of the inductor current, can achieve the power factor correction and meet the IEC 61000-3-2. However, the switching frequency is variable in a line cycle, and the design of the inductor and electromagnetic interference filter as well as the power component selection is deteriorated. In this paper, a novel constant frequency control method is proposed for the converter by modulating the on-time of the switch. Compared with the traditional variable frequency control, the proposed control scheme achieves a constant switching frequency in a line cycle, which simplifies the design of the power devices, especially the magnetic components. Furthermore, the switching frequency and the rms value of the inductor current are also reduced, which contributes to a higher efficiency. [ABSTRACT FROM AUTHOR]

DC circuit breaker plays an important role in the reliability of HVdc system, but the large number of expensive press-pack insulated-gate bipolar transistors (IGBTs) is used at present, which is a serious impediment to HVdc development. Thus, the low-price integrated gate commutated thyristor (IGCT) becomes a promising alternative device. This letter presents a low-cost HVdc circuit breaker with high current breaking capability based on IGCTs. The topology and principle of the proposed HVdc circuit breaker are introduced at first. Then, the parameter design is analyzed. A scaled-down test successfully demonstrates the high current breaking capability of 15 kA. In the end, the cost comparison shows that this scheme can achieve 61.8% cost reduction of the commutation branch. [ABSTRACT FROM AUTHOR]