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The characteristic nondestructive single-event latchup (SEL) phenomena, 'local' and 'pseudo' SELs, were identified in complex digital Large Scale Integrations (LSIs) by using a photo-emission microscope. Usually, SELs are detected as an abrupt increase of power supply current. However, it was experimentally demonstrated that the simple method could not give sufficient information to determine if it is a destructive or a nondestructive phenomenon. If the observed SELs can be confirmed as a nondestructive phenomenon with a certain confidence level, a simple circumvention technique can be effectively employed and the chance to utilize attractive commercial devices will be greatly enhanced. The SEL test method to identify this type of LSI was discussed and a new procedure was proposed. Index Terms--Non-destructive, photo-emission microscope, single-event latchup (SEL), system-on-a-chip (SoC).

We designed logic cells hardened for single-event upsets/singe-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKI's 0.15 [micro]m fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR. Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/[cm.sup.2]). Index Terms--Commercial process, fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI), hardness-by-design (HBD), single-event transient (SET), single-event upset (SEU).

We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 [micro]m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs. Index Terms--Commercial process, hardness-by-design, latch and flip-flop cell, single-event effect

A new failure mode that is attributable to the bulk damage caused by single protons has been reported in 256-Mbit SDRAMs. The refresh rate required to retain memorized data was measured as a typical parameter to detect the effect. We performed the proton irradiation test and discussed results regarding the influence of this failure. Index Terms--Bulk damage, protons, radiation, retention time, sunchronous dynamic random access memory (SDRAM).

The origin of damage causing radiation in a beam blanking scanning electron micrograph (BBSEM) was identified and removed for single-event upset (SEU) testing. The improved BBSEM was successfully used to locate SEU sensitive areas in highly integrated silicon devices. Index Terms--Beam blanking, ion track structure, multiple bit upset (MBU), scanning electron micrograph.

Single-Event Burnout (SEB) of bipolar junction transistors (BJTs) has been observed nondestructively. It was revealed that all the NPN BJTs, including small signal transistors, With thinner epitaxial layers were inherently susceptible to the SEB phenomenon. It was demonstrated that several design parameters of BJTs were responsible for SEB susceptibility. Additionally, destructive and nondestructive modes of SEB were identified.

Single event burnout (SEB) phenomenon of power MOSFETs caused by nuclear reactions with incident heavy ions has been probed experimentally. 520MeV Kr and 3536MeV Xe ions having the same LET were used as incident ions for the experiment. The observed SEB threshold voltage was quite different for both ions. Detailed analysis revealed that the Xe ions can produce excess charge as a result of nuclear reactions with Si atoms. The result suggests that usual SEB immunity test as a function of LET is not adequate for high voltage devices that have much larger sensitive volume.

Total dose effect on the soft-error susceptibility of 64kbit CMOS SRAM has been investigated by using the single ion microprobe technique which enables us to get a map of soft-error sensitivity in a memory cell by hitting a micron-size area with single ions. The effects of the ion dose on the susceptibility of each error-sensitive site have been evaluated. The errors due to the upset of p-MOSFETs have become more susceptible at higher dose while that of the n-MOSFETs less susceptible. One of the origins of the errors are the negative threshold voltage ([V.sub.th]) shifts of the MOSFETs which are caused by oxide trapped charges. Displacement damage induced by ion irradiation also affects the susceptibility to the soft-error.

A new characterization technique for single event burnout (SEB) of power MOSFETs has been developed. The technique is based on a pulse-height analyzer system for charge collection measurement with a modified charge-sensitive amplifier which has very wide dynamic range. The data obtained by this technique gives detailed information about the SEB mechanism of power MOSFETs. The experimental data suggested a position independent charge collection mechanism along an ion track, and a new parameter for SEB hardness was proposed.

New types of multiple-bit upset (MBU) modes have been identified in high-density DRAMs (16 Mbit and 64 Mbit). The identification of the mechanisms responsible for the new modes is based on detailed physical bit-map analysis.

We designed logic cells hardened for single-event upsets/singe-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKI's 0.15 μm fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR. Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/cm²). [ABSTRACT FROM AUTHOR]

We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 pm Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs. [ABSTRACT FROM AUTHOR]

We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 μm CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs. [ABSTRACT FROM AUTHOR]

A new failure mode that is attributable to the bulk damage caused by single protons has been reported in 256-Mbit SDRAMs. The refresh rate required to retain memorized data was measured as a typical parameter to detect the effect We performed the proton irradiation test and discussed results regarding the influence of this failure. [ABSTRACT FROM AUTHOR]