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A new method for enhancing the sensitivity of the Floating Gate DOSimeter (FGDOS) has been investigated. By increasing the electric field in the silicon dioxide, it is possible to improve the fractional yield of collection of the electron–hole pairs, thus to increase the device’s sensitivity. In particular, a sensitivity enhancement implies a proportional improvement of the sensor’s dose resolution. Such an amelioration would dramatically improve the dosimeter’s performance in low dose rate environments, especially when only short time windows are available for measurements. Moreover, a higher electric field in the floating gate oxide makes for an improved sensitivity degradation rate throughout the device’s radiation lifetime. Results, both from analog and digital test chips, are presented, proving the effectiveness of the enhancement and its effect on the FGDOS’ sensitivity degradation rate. Finally, both aspects are discussed and explained from a theoretical point of view. [ABSTRACT FROM AUTHOR]

This article investigates the device variability induced by the total ionizing dose (TID) effects in a commercial 16-nm bulk nFinFETs, using specially designed test structures and measurement procedures aimed at maximizing the matching between devices. DC static characteristic measurements show that below 100 Mrad(SiO2) the device variability is slightly affected by the total accumulated dose. However, when the total dose reaches 100 Mrad(SiO2), the device variability increases significantly showing a correlation with pre-irradiation electrical responses of the devices. Transistors characterized by higher drain current exhibit the worst TID degradation. This phenomenon is likely due to the impact of random dopant fluctuations on the TID effects and/or to variations in the hydrogen concentration responsible for the TID-induced interface traps. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

This article studies the apparition and the fast annealing of a leakage current in p- and n-MOS transistors and structures. This leakage current is observed for total ionizing doses (TIDs) of 50 Mrad(SiO2) and above and anneals rapidly within the hours following the end of irradiation. An extensive set of specially designed and dedicated structures are used to study this phenomenon. In particular, the article presents the effects of the dose rate, the transistor type (n or p), the drain–source voltage, or the bias during annealing. Results show that the observed transient leakage current is an intensification followed by fast annealing of the generation current inside the drain and source depletion regions. It appears that this generation leakage current most likely originates from the creation of positive charges in the thick oxides of the devices, that is, the shallow trench isolation (STI) and the pre-metal dielectric (PMD), and it generally anneals at ambient temperature in less than 12 h after irradiation. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) responses are investigated for 3-D-sequentially integrated fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Strong layer-to-layer coupling of TID response is observed. The simultaneous application of positive bias to the gate of the bottom-layer device and negative bias to the top-layer device leads to the maximum enhancement of positive charge trapping in the top-layer device and the intermediate dielectric layer. This enhancement is due to the upward-directed electric field in the intermediate dielectric layer under these bias conditions. In contrast, electrostatic shielding prevents the gate bias of the top-layer device from affecting the response of the bottom-layer device, as confirmed by experiments and technology computer-aided design (TCAD) simulations. Effects of layer-to-layer coupling are less significant for postirradiation-biased annealing. [ABSTRACT FROM AUTHOR]

Radiation-induced leakage current degradations for SiC power MOSFETs are investigated by 181Ta ion irradiation. An ion flux-related leakage degradation is reported for the first time. It is manifested as a more significant leakage current under higher flux irradiation than that under low flux irradiation, even though the total fluence is the same. Emission microscope (EMMI) results show that more leakage paths are formed for high flux irradiation. The drain bias during irradiation is another key fact to affect the radiation-induced leakage degradation. The leakage only occurs when the drain bias is larger than 300 V for flux = 1000/cm $^{2}\cdot \text{s}$ irradiation. An interesting phenomenon is that although radiation-induced leakage is not observed at 200 V with ion flux of 1000/cm $^{2}\cdot \text{s}$ , leakage appears when the ion flux increases to 6000/cm $^{2}\cdot \text{s}$. A multi-ion interaction theory is proposed to explain the above phenomenon. The mechanisms of these phenomena are also proved by TCAD simulations. [ABSTRACT FROM AUTHOR]

Impact of high total ionizing dose (TID) irradiation on stability of 65 nm static random-access memory (SRAM) cells is investigated in this article. The stability of 65 nm SRAM cells is measured not only by the SRAM array but also by the independent cell test structure. The test chip has been subjected to a TID irradiation of 200 Mrad(Si). Experimental results show a reverse data pattern imprinting effect, i.e., irradiated 65 nm SRAM cells are more inclined to the complementary TID data pattern, and the above asymmetry of irradiated 65 nm SRAM cells is due to the bias-dependent shift in threshold of the pull-down nMOSFETs constituting the SRAM cell. [ABSTRACT FROM AUTHOR]

In this article, we provide an analytical model for the total ionizing dose (TID) effects on the bit error statistics of commercial flash memory chips. We have validated the model with experimental data collected by irradiating several commercial NAND flash memory chips from different technology nodes. We find that our analytical model can project bit errors at higher TID values [~20 krad (Si)] from measured data at lower TID values [<1 krad (Si)]. Based on our model and the measured data, we have formulated basic design rules for using a commercial flash memory chip as a dosimeter. We discuss the impact of NAND chip-to-chip variability, noise margin, and the intrinsic errors on the dosimeter design using detailed experimentation. [ABSTRACT FROM AUTHOR]

The effects of total ionizing dose (TID) on MOSFETs fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology are analyzed. TID causes positive-trapped charge to accumulate in transistor isolation regions [e.g., the buried oxide (BOX)], thereby generating negative TID-induced threshold-voltage shifts $\Delta V_{\mathrm {th}}$ that facilitate nMOSFET turn-on and inhibit pMOSFET turn-on. Back-gate biasing options in the technology can be used to offset the threshold-voltage shifts. Applying a bias to the back gates of MOSFETs in a conventional-well back-gate configuration mitigates TID-induced $\Delta V_{\mathrm {th}}$ in nMOSFETs (where a negative bias is applied to the P-well back-gate), while enhancing the same in pMOSFETs (where a positive bias is applied to the N-well back-gate). To mitigate and potentially reverse TID-induced $\Delta V_{\mathrm {th}}$ of both nMOSFETs and pMOSFETs simultaneously, a single back-gate bias can be applied to MOSFETs in a common isolated P-well back-gate configuration. 3-D technology computer-aided design (3-D TCAD) device simulation results of the 22-nm FD-SOI technology confirm the conventional-well circuit-level radiation response and support the effectiveness of using the common isolated P-well back-gate configuration for TID mitigation. These results justify the utility of dynamically tuning back-gate bias according to actively monitored TID-induced $\Delta V_{\mathrm {th}}$ feedback. [ABSTRACT FROM AUTHOR]

This article reviews the effects of applied bias and temperature on Si/SiO2 interface-trap buildup and annealing rates. Electrical and spectroscopic methods are described to estimate interface-trap densities at oxidized Si surfaces, in MOS capacitors and transistors, and in linear bipolar devices. Illustrative results provide insights into the kinetics and energetics of interface-trap annealing. Interface traps in MOS and linear bipolar devices anneal much more easily at 0 V bias than at positive or negative applied bias. Hydrogen transport and reactions play critical roles in interface-trap buildup and annealing processes. The complex interplay between H2 diffusion and H+ drift is illustrated via coupled experimental and theoretical studies. Interface-trap annealing imposes significant constraints on hardness-assurance techniques. Current MOS standard tests that incorporate accelerated aging at elevated temperature at worst case, static, positive bias enable successful assessment of MOS devices in low-dose-rate environments. However, it is not similarly possible to use elevated-temperature irradiation and/or annealing at worst case, 0 V bias to predict low-dose-rate response for linear bipolar devices and ICs. Temperature-switching during irradiation appears to be a promising approach to address this issue. [ABSTRACT FROM AUTHOR]

At advanced technology nodes, single-event (SE) cross sections from logic circuits contribute significantly to the total SE cross section in sequential circuits operating at high frequencies. SE cross section for logic circuits is experimentally investigated at the 7-nm bulk FinFET node. Results for threshold voltage options, supply voltage, frequency, and particle linear energy transfer (LET) are presented and compared with the 16-nm node. The model presented and validated in this work will assist designers in estimating logic SE error contributions for a variety of applications and operating conditions. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized under dynamic and static test conditions through changes in ring oscillator (RO) frequencies, leakage currents, and inverter delays. Results from total-dose exposures using the ARACOR X-ray machine showed that static conditions represented the worst case conditions. Higher operating frequencies resulted in increased leakage currents and inverter delays after irradiation. The rate of change for leakage current was inversely proportional to frequency during exposure. The rate of change for inverter delay was directly related to frequency during TID exposure. Overall, degradations in circuit-level parameters (logic gate delays and operating current) were less than 1% for TID exposures of 435 krad(SiO2). [ABSTRACT FROM AUTHOR]

Negative-bias-stress and total-ionizing-dose (TID) effects in deeply scaled Ge-gate-all-around (GAA) nanowire (NW) devices are characterized for different biasing conditions. Negative-bias-stress-induced degradation in Ge GAA device originates primarily from the interface- and border-trap generation. Devices stressed at high gate voltage show rapid initial degradation and quick saturation dominated by interface-trap generation. Radiation-induced OFF-state leakage current in Ge GAA NWs increases with dose due to enhanced band-to-band tunneling (BTBT) caused by charge trapping in the shallow trench isolation (STI). [ABSTRACT FROM AUTHOR]

Effects of ~35 years of aging during storage are investigated on the radiation response and 1/ $f$ noise of Oki nMOS and pMOS transistors with high oxygen vacancy densities in SiO2. Short-term interface-trap buildup during irradiation is enhanced significantly, relative to that observed in 1989, 1997, and 2008. In contrast, a similar latent interface-trap buildup is observed for aged pMOS devices irradiated and annealed at room and elevated temperatures at positive bias in this and earlier studies. The significant latent interface-trap buildup is observed for nMOS devices irradiated at 0 V and annealed at room and elevated temperatures under positive bias, a condition not evaluated in prior work. Results strongly suggest that latent interface-trap buildup is due to H2 diffusion and dissociation at charged or dipolar O vacancies in SiO2, followed by proton transport to the Si/SiO2 interface and reactions with Si–H complexes. Models that attribute latent interface-trap buildup to long-term proton trapping at O vacancies in SiO2 appear to be ruled out by these results. Additional insight is provided into mechanisms of postirradiation interface- and border-trap buildup after long-term MOS device storage. [ABSTRACT FROM AUTHOR]

This work presents measured data showcasing neutron-radiation-induced single-event transient (SET) pulse widths in distinct standard logic gate types, together with a detailed analysis on the choice of design parameters impacting the corresponding sampled pulsewidth distributions. The SET pulsewidth distributions are obtained from a high-density, array-based characterization vehicle, implemented in 65-nm planar CMOS and 16-nm FinFET processes, featuring a tunable, high-resolution pulse shrinking chain together with a closely embedded sampling circuit to avoid width distortion effects. The proposed macro uses standard logic gate chains in varying lengths, threshold voltages ($V_{\mathrm {TH}}$), and transistor width flavors as the devices under test (DUTs). The measured irradiation data for a range of operating voltages from nominal down to near-threshold reveal the relative impact of the chosen design parameters such as VDD, $V_{\mathrm {TH}}$ , device width, and the logic chain length and their interplay, impacting the overall soft error susceptibility and the sampled pulsewidth distributions among the different standard gate types. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) degradation is caused by radiation-induced charge buildup in oxides. Radiation hardening of silicon-on-insulator (SOI) devices with deep submicrometer nodes or nanonodes is mainly concerned with the field oxide and buried oxide. In this article, a back-channel adjustment technique for TID hardening is proposed. The technique is compatible with the 130-nm partially depleted silicon on an insulator (PDSOI) commercial process with no extra effort applied to the design. After testing the key electrical parameters and characterizing the radiation tolerance of the typical T-gate I/O nMOS devices, the results show that the radiation tolerance of the devices can reach more than 1 Mrad(Si) with the back-channel adjustment technique, and electrical performance is comparable to that of commercial process devices. [ABSTRACT FROM AUTHOR]

Within-wafer total ionizing dose (TID) response variability on buried oxide (BOX) layer of silicon-on-insulator (SOI) technology is investigated in this article. TID response variability is measured by the threshold voltage and OFF-state leakage of transistors evenly distributed on the wafer locations. Experimental results show the larger standard deviation of threshold voltage and OFF-state leakage distribution for irradiated devices than unirradiated devices, illustrating the within-wafer TID response variability. The hole traps variation in the BOX layer is responsible for the within-wafer TID response variability of SOI technology. Moreover, a data analysis method according to T-distribution is proposed to obtain the within-wafer TID response variability by the sampling testing results of limited wafer locations. Our data show that the T-distribution method is reasonable to assess the TID-induced variability of a process when only a few samples are available. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized through changes in ring oscillator (RO) frequencies and current as a function of $V_{\mathrm {DD}}$ to model delay and power degradations in digital circuits. At the 7-nm node, tests show that gate delay decreased, and power consumption increased as TID increased. Percent increase in parameter degradations shows an inverse relationship with supply voltage, while percent increase in power consumption shows a direct relationship with supply voltage. Annealing at room temperature did not affect degradations. Circuit-level degradations for the 7-nm technology were less than 1% after TID exposure of 380 krad(SiO2). These TID exposure results will provide insight to designers about circuit-level parameters of interest concerning the 7-nm technology node. [ABSTRACT FROM AUTHOR]

The SuperKEKB accelerator in Tsukuba, Japan is providing e+e− beams for the Belle II experiment since March 2019. To deal with the aimed peak luminosity being 40 times higher than the one recorded at Belle, a pixel detector based on DEPFET technology has been installed. It features a long integration time of 20 μs resulting in an expected data rate of 20 GByte/s (160 GBit/s) at a maximum occupancy of 3%. To deal with this high amount of data, the data-handling hub (DHH) has been developed. It contains all necessary functionality for the control and readout of the detector. In this article, we describe the architecture and features of the DHH system. Further, we will show the key performance characteristics after one year of operation. [ABSTRACT FROM AUTHOR]

This article demonstrates the total ionizing dose (TID) impact on a NAND flash memory-based physical unclonable function (PUF). We used commercial-off-the-shelf flash memory chips to generate PUF. The flash chip is irradiated with Co-60 gamma rays up to 10 krad(Si). The irradiated chip shows significant accuracy degradation (bit error ~ 12%) of the flash-PUF. We show that TID-induced trapped charges in the oxide alter the intrinsic cell properties causing accuracy degradation of flash-PUF. We propose two independent techniques to improve the PUF accuracy under radiation environment. The first technique relies on electrical annealing which compensates the trapped charges by program stressing. The second technique uses radiation compensation method by adaptive PUF generation process. Our experimental results show that the accuracy degradation can be as low as 1.5% for TID up to 10 krad(Si) with these radiation mitigation techniques. [ABSTRACT FROM AUTHOR]

Impact of total ionizing dose (TID) on the within-wafer variability of radiation-hardened (RH) silicon-on-insulator (SOI) wafers is investigated in this article. The within-wafer variability is measured by the front gate and back gate I – V characteristics of the transistors in 32 dies evenly distributed on wafer locations. The experimental results show the complex dependence of the within-wafer variability on TID: the within-wafer variability of RH SOI wafer is first weakened by TID irradiation and then rebounds. The evolution of net trapped charge induced by TID in buried oxide (BOX) is affected by positively charged silicon nanoclusters introduced by silicon ion implantation, which is responsible for the above complex dependence. Moreover, radiation hardness assurance method relying on sample testing of limited wafer locations is discussed, which can give the reasonable estimation of the within-wafer variability on TID irradiated devices. [ABSTRACT FROM AUTHOR]

During heavy-ion experiments, the single-event gate rupture (SEGR) effects can still be observed in the vertical double-diffused power MOSFET (VDMOS) with radiation-hardened cells. Fault analysis demonstrates that the hot spots locate at the termination of the VDMOS. Then, several mitigation solutions for termination structure are discussed comprehensively by means of TCAD simulations. Finally, a combined hardness method with horizontally extending P+ region and adding floating N+ region is proposed. It is effective to reduce the electric field of gate oxide to below the calculated critical field, without additional masks and process steps. [ABSTRACT FROM AUTHOR]

Bulk 14-nm FinFET technology was irradiated in a heavy-ion environment (42-MeV Si ions) to study the possibility of displacement damage (DD) in scaled technology devices, resulting in drive current degradation with increased cumulative fluence. These devices were also exposed to an electron beam, proton beam, and cobalt-60 source (gamma radiation) to further elucidate the physics of the device response. Annealing measurements show minimal to no “rebound” in the ON-state current back to its initial high value; however, the OFF-state current “rebound” was significant for gamma radiation environments. Low-temperature experiments of the heavy-ion-irradiated devices reveal increased defect concentration as the result for mobility degradation with increased fluence. Furthermore, the subthreshold slope (SS) temperature dependence uncovers a possible mechanism of increased defect bulk traps contributing to tunneling at low temperatures. Simulation work in Silvaco technology computer-aided design (TCAD) suggests that the increased OFF-state current is a total ionizing dose (TID) effect due to oxide traps in the shallow trench isolation (STI). The significant SS elongation and ON-state current degradation could only be produced when bulk traps in the channel were added. Heavy-ion irradiation on bulk 14-nm FinFETs was found to be a combination of TID and DD effects. [ABSTRACT FROM AUTHOR]

In this article, five different cell placement structures of a vertical inverter chain were designed in a commercial bulk FinFET technology to investigate the effect of cell placement on a single-event transient (SET) pulse. 3-D TCAD mixed-mode simulation indicated that the cell placement has a significant effect on SET pulsewidths. Heavy-ion experiments at Cyclotron in the China Institute of Modern Physics in Lanzhou also indicated that the effect of cell placement on the SET pulse is obvious. The experiment also indicated that the effect of cell placement on P-hit SET is larger than that on N-hit SET, and charge sharing in vertical was becoming as important as that in horizontal. [ABSTRACT FROM AUTHOR]

This article investigates the effect of ultra-high total ionizing dose up to 450 Mrad(SiO2) on 180-nm MOSFETs for analog applications. In particular, it studies the influence of the transistor size, design, type, bias, and the annealing on radiation-induced degradation. It studies the radiation effects on three parameters: the drive current, the threshold shift, and the leakage current. First, it reveals radiation-induced short-channel effects (RISCEs), which were until now only observed on more advanced technology nodes, and highlights that its mechanism of apparition differs from these advanced nodes. Second, it highlights the importance of bias during irradiation, not only on the magnitude of these effects but also on the type of defects at their origin. In particular, it demonstrates that the bias during irradiation plays a major role in the n-MOS–p-MOS dissymmetry. Third, it points out the capacity of the ELT and the butterfly rad-hard designs to mitigate the radiation-induced narrow channel effect (RINCE), the LPT, and several other radiation-related issues. Finally, it shows that the 3.3-V designs, compared to the 1.8-V designs, present a larger sensibility to radiation due to their thicker gates, but that they could stay a better choice for analog applications up to 400 Mrad(SiO2), thanks to their larger voltage range. [ABSTRACT FROM AUTHOR]

Accelerated terrestrial neutron irradiations were performed on different commercial SiC power MOSFETs with planar, trench, and double-trench architectures. The results were used to calculate the failure cross sections and the failure-in-time (FIT) rates at sea level. Enhanced gate and drain leakage were observed in some devices which did not exhibit a destructive failure during the exposure. In particular, a different mechanism was observed for planar and trench gate MOSFETs, the first showing a partial gate rupture with a leakage path mostly between the drain and the gate, similar to what was previously observed with heavy ions, while the second exhibiting a complete gate rupture. The observed failure mechanisms and the postirradiation gate stress (PIGS) tests are discussed for different technologies. [ABSTRACT FROM AUTHOR]

Total ionizing dose response of 14-nm bulk-Si FinFETs has been studied with a specially designed test chip. The radiation testing shows evidence of interface trap build-up on 14-nm Bulk FinFET technologies. These defects created in the isolation layer give rise to a new radiation-induced leakage path which might lead to a reliability issue in CMOS technologies at or below the 14-nm node. TCAD simulations are performed and an analytical model for TID-induced leakage current is presented to support analysis of the identified TID mechanism. TCAD simulation and analytical model results are consistent with the experimental data. [ABSTRACT FROM AUTHOR]

MOS transistors in 65-nm CMOS technology exposed to ultrahigh total ionizing dose (TID) levels show clear evidence of a true dose-rate (DR) dependence. In order to assess the impact of this effect and to understand its origin, an extensive measurement campaign has been carried out at different DRs, different temperatures, and different biases. Both nMOS and pMOS devices with different sizes and geometries were studied. The results obtained clearly show that the DR sensitivity of these devices is due to mechanisms that occur in the spacer insulators. Spacers have only recently been identified as an important element in the radiation response of MOS devices exposed to ultrahigh doses and the mechanisms causing their DR sensitivity appear to be largely compatible with the models developed to explain enhanced low dose-rate sensitivity (ELDRS) in linear bipolar transistors. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated for 22-nm fully-depleted silicon-on-insulator (FDSOI) and 14-nm bulk FinFET charge-trap memory transistors. Electron trapping in the gate dielectric establishes the programmed memory state for both silicon on insulator (SOI) and bulk devices. To first order, ionizing radiation does not interact strongly with programing-induced charges in the gate dielectric for either device type. Hole trapping in the buried oxide dominates the TID response of the 22-nm FDSOI devices. The 14-nm bulk devices with two fins and total effective fin widths of 150 nm are minimally affected by TID, but the subthreshold leakage of devices with 40 fins and total effective fin widths of $3~\mu \text{m}$ increases with increasing TID. When devices are programmed or reprogrammed after irradiation, significant increases in subthreshold slope are observed due to the generation of interface traps, border traps, and/or charge lateral nonuniformities. [ABSTRACT FROM AUTHOR]

This article analyzes the data corruption pattern in the shared pages of multi-level cell (MLC) 3-D NAND memory under ionizing radiation from a Co-60 gamma-ray source for up to 20 krad(Si) dose. The results show that the radiation-induced error pattern between the shared pages follows a unique correlated behavior. We also find that the error locations within a given page remain uncorrelated, meaning that the occurrence of an error does not force a cluster of errors under ionizing radiation. [ABSTRACT FROM AUTHOR]

In this article, we have evaluated the Read-Retry (RR) functionality of the 3-D NAND chip of multilevel-cell (MLC) configuration after total ionization dose (TID) exposure. The RR function is typically offered in the high-density state-of-the-art NAND memory chips to recover data once the default memory read method fails to correct data with error correction codes (ECCs). In this work, we have applied the RR method on the irradiated 3-D NAND chip that was exposed with a Co-60 gamma-ray source for TID up to 50 krad (Si). Based on our experimental evaluation results, we have proposed an algorithm to efficiently implement the RR method to extend the radiation tolerance of the NAND memory chip. Our experimental evaluation shows that the RR method coupled with ECC can ensure data integrity of MLC 3-D NAND for TID up to 50 krad (Si). [ABSTRACT FROM AUTHOR]

A special total-ionizing-dose-induced short channel effect in thin-film partially depleted silicon-on-insulator (PDSOI) technology is found. Short devices suffer more significant total-ionizing-dose-induced threshold voltage shift of the front-gate main transistor. The devices under pass-gate (PG) bias show worse threshold voltage shift of the front-gate main transistor than the devices under ON bias, which reveal that the trapped charges in the buried oxide layer are more responsible for these phenomena. Through the simulation of the electric field under PG bias by TCAD, we found that devices with different lengths can be uniformly divided into four regions. Then we combined the partially full depletion model with charge-sharing model and made a qualitative analysis of this effect. On this basis, we proposed a quantitative analysis model. Through this model, we can calculate the threshold voltage shift of the front-gate main transistor through the threshold voltage shift of back-gate main transistor. [ABSTRACT FROM AUTHOR]

In this article, the total ionizing dose (TID) effect is investigated in the 30-V split-gate trench (SGT) Vertical double diffused MOSFET (VDMOS). The complex trench structure, including gate oxide, split-gate oxide, and isolation oxide, is carefully studied to reveal the degradation mechanisms. Due to the multioxidation and annealing processes, the trench structure suffers serious oxide defeats. The analytical result shows a larger trapping efficiency (ƒot) compared to the planar gate technology, leading to significant Vth shifts and subthreshold leakage. Meanwhile, irradiation-induced trapped charges in the split-gate oxide have a great influence on the electric field profile in bulk, which gives rise to breakdown voltage (BV) degradation. The experimental result shows that BV presents a gradient descent and drops to as low as 14 V at 100 krad(Si). Through TCAD simulation and analytical calculation, these TID responses are evaluated, and three approaches have been proposed for the radiation hardness of SGT VDMOS. [ABSTRACT FROM AUTHOR]

Heavy-ion microbeams are employed for probing the radiation-sensitive regions in commercial silicon carbide (SiC) vertical double-diffused power (VD)-MOSFETs with micrometer accuracy. By scanning the beam spot over the die, a spatial periodicity was observed in the leakage current degradation, reflecting the striped structure of the power MOSFET investigated. Two different mechanisms were observed for degradation. At low drain bias (gate and source grounded), only the gate-oxide (at the JFET or neck region) is contributing in the ion-induced leakage current. For exposures at drain–source bias voltages higher than a specific threshold, additional higher drain leakage current is observed in the p-n junction region. This provides useful insights into the understanding of basic phenomena of single-event effects in SiC power devices. [ABSTRACT FROM AUTHOR]

The combined effects of electrical stress and neutron irradiation of the last generation of commercial discrete silicon carbide power MOSFETs are studied. The single-event burnout (SEB) sensitivity during neutron irradiation is analyzed for unstressed and electrically stressed devices. For surviving devices, a comprehensive study of the breakdown voltage degradation is performed by coupling the electrical stress and irradiation effects. In addition, mutual influences between electrical stress and radiative constraints are investigated through TCAD modeling. [ABSTRACT FROM AUTHOR]

The standard and layout-hardened D filp-flops (DFFs) named DFF1–6 were designed and manufactured based on an advanced 22-nm ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) technology. Heavy-ion irradiation results indicate that FD-SOI technology has contributions to radiation hardness and the hardened DFFs have higher single-event upset (SEU) tolerance than the standard DFF. The upsets induced by the embedded SET targets are strongly dependent on the testing frequency. The layout separating the dual interlocked storage cell (DICE) structure can prevent the direct occurrence of SEU in flip-flop cells, and upsets were removed completely in two-fold DICE structure DFFs. [ABSTRACT FROM AUTHOR]

The design methodology based on standard cells is widely used in a broad range of very-large-scale integration (VLSI) applications. Furthermore, several optimization algorithms can be employed to address different constraints such as power consumption or reliability. This paper evaluates the implications of the usage of complex logic cells from a 45-nm standard-cell library to the single-event transient (SET) sensitivity under heavy ions. Results show that even though a reduction in the layout area is obtained when adopting complex logic gates, a slight reduction in the total sensitive area of the circuit is observed. Moreover, the effectiveness of the logical masking can be suppressed, leading to a higher SET cross section for high particle linear energy transfer (LET). [ABSTRACT FROM AUTHOR]

High sensitivity of silicon-carbide (SiC) power MOSFETs has been observed under heavy-ion irradiation, leading to permanent increase of drain and gate leakage currents. The electrical postirradiation analysis confirmed the degradation of the gate oxide and the blocking capability of the devices. At low drain bias, the leakage path is formed between drain and gate, while at higher bias the heavy-ion-induced leakage path is mostly from drain to source. An electrical model is proposed to explain the current transport mechanism for heavy-ion degraded SiC power MOSFETs. [ABSTRACT FROM AUTHOR]

The damage sites introduced by single-event gate rupture (SEGR) in Si vertical power MOSFETs were physically analyzed to clarify their location and structures. It was found that the damage sites were located on the neck region between p-body diffusions as expected, and the gate oxide was replaced by Si to electrically connect the gate poly-Si and Si-substrate at the damage sites. As a result, the complicated electrical properties observed on the damaged device were successfully modeled by assuming an Si spike at the damage site in device simulations. It was also suggested that the postgate-stress test with applied voltage higher than that applied during the SEGR test might have forced additional thermal stress on the damage site and have caused the failure attributable to the postgate-stress test itself. [ABSTRACT FROM AUTHOR]

The interface quality between the gate dielectric and germanium (Ge) channel plays a crucial role for Ge MOSFETs. The impact of different interface passivation techniques on the total ionizing dose (TID) effect of Ge pMOSFET with enclosed-layout and Al2O3/TiN gate-stack is experimentally investigated under different bias conditions. The N-passivation and O-passivation of Ge pMOSFETs are realized by nitrogen-plasma-passivation (NPP) and rapid-thermal-oxidation, respectively. Negative threshold voltage ($V_{\text {th}}$) shift and positive $V_{\text {th}}$ shift are observed for devices irradiated under on-state and TG-state, respectively, which are partially due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) stresses. The NBTI and PBTI effects are evaluated to obtain “pure” $V_{\text {th}}$ shifts induced by TID irradiation. The O-passivated Ge pMOSFETs show larger pure radiation-induced $V_{\text {th}}$ shifts than N-passivated devices, which is attributed to less irradiation-induced border trap density in the N-based interfacial layer (IL) than the O-based IL. Therefore, N-based IL is more suitable for Ge MOSFET than the O-based IL from a perspective of radiation hardness. The results may provide interface material-design guideline for radiation-hardened and high-performance Ge MOSFET fabrication. [ABSTRACT FROM AUTHOR]

A method is presented to enhance single-event transient (SET) measurements by overcoming a common experimental limitation of minimum measurable pulse widths. As technology scales, SETs decrease in width and measurement circuits fundamentally cannot capture every fast transient capable of causing an error. A method has been developed to overcome this limitation by using a latch as a feedback-assisted fast transient capture circuit. Single-event upset (SEU) data are combined with SET data to extend pulsewidth acuity such that pulses faster than the minimum measurable SET pulsewidth are extracted. The method has been applied for a 14-/16-nm bulk FinFET technology node and predictions for logic single-event cross section reveal the impact of fast transients on the radiation response of logic circuits. Results including the extracted fast transients represent upper bound SEU cross sections. For high linear energy transfer (LET) particle irradiation, accounting for fast transients using the developed method results in negligible variation in logic SE cross section. However, for low LET particle irradiation, the method results in an order of magnitude increase in logic SE cross section. [ABSTRACT FROM AUTHOR]

Bulk and silicon-on-insulator (SOI) n-channel FinFETs with fin widths of 15–40 nm and channel lengths of 45 and 1000 nm were irradiated with 1.8 MeV protons at temperatures of 295 and 90 K. Bulk and SOI FinFETs show improved transconductance and steeper subthreshold slopes before irradiation at 90 K than at 295 K. Increased off-state leakage currents are observed for longer channel bulk FinFETs for doses above 300–500 krad (SiO2) for 295 and 90 K irradiation, and at lower doses for shorter channel devices. Threshold-voltage shifts for irradiation up to 1 Mrad(SiO2) are greater for SOI devices at 90 K than at 295 K due to enhanced charge trapping in the buried oxide (BOX). TCAD simulations provide insight into radiation-induced trapped-charge densities in the SOI devices. [ABSTRACT FROM AUTHOR]

This paper evaluates the error rate of a memory-bound application implemented in different commercial-off-the-shelf multicore and many-core processors. To achieve this goal, two quantitative experiments are performed: fault-injection campaigns and radiation ground testing. In addition, this paper proposes an approach for predicting the application error rate by combining the results issued from both types of experiments. The usefulness of the approach is illustrated by three case studies implemented in processors having different manufacturing technologies and architectures: 45-nm silicon-on-insulator (SOI) free-scale P2041 quad-core processor, 65-nm CMOS Adapteva Epiphany multicore processor, and 28-nm CMOS Kalray multipurpose processing array-256 many-core processor. The reliability of the processors for avionics is obtained from their experimental error rates extrapolated to avionic altitudes. Reliability curves are plotted for observing the prediction accuracy. A comparison of the failure in time of the selected processors shows that the greater single-event effect vulnerability of CMOS technology compared with the SOI one can be compensated with the implementation of effective error detection and correction. These protection mechanisms allow the use of CMOS devices having huge memory capacity in applications operating in severe radiation environments. [ABSTRACT FROM AUTHOR]

Analysis of temporal masking effects of single-event upsets (SEUs) on master–slave flip-flops (FFs) is provided, considering the difference of SEU cross sections between master and slave latches. An improved model of temporal masking effects of SEUs in master–slave FFs is proposed and demonstrated through alpha-particle single-event effect (SEE) experiments. Based on the improved model, an effective and accurate methodology to quantitatively evaluate single-event transient and SEU-induced error cross sections of FF chains is proposed. Implications of SEE hardening for sequential circuits are discussed. [ABSTRACT FROM AUTHOR]

Thanks to its compact structure, mechanical endurance, and low bias voltage, the silicon photomultiplier (SiPM) can be used in small-size applications which require reduced power consumption. In order to detect the light intensity as low as a single photon, the front-end electronics has to amplify and shape the signal of the photodetector. The low-power design cannot impair the performance of readout electronics or limit the capabilities of the SiPM itself. This paper presents a two-channel integrated circuit (IC) designed in Austria Mikro Systeme CMOS 350-nm technology dedicated for the SiPM-based applications. The input stage is a super-common-gate architecture. Each channel of the IC consists of an amplifier and a peak detector with an offset reduction circuit. The power consumption of the single channel is less than 3 mW from the single voltage supply (3.3 V). Moreover, the number of channels of the IC can be easily increased thanks to small dimensions of the circuit. This paper presents a detailed analysis of the IC including: noise performance with adjustment of the input transistor’s size, transient and dc simulations of the amplifier and the peak detector, and the introduction of a simple offset reduction technique for the peak detector. The measurement results obtained with two SiPM detectors are presented. [ABSTRACT FROM AUTHOR]

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency. [ABSTRACT FROM PUBLISHER]

At the gigahertz range of frequencies, contribution of combinational logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any combinational logic circuit. Estimated logic SEU cross section matches well with the measured logic SEU cross section. Estimated logic SEU cross section results obtained with the proposed method are within $2\times $ average error when compared to the experimentally measured logic SEU cross section. This method only needs to be calibrated once for use at a given technology node. [ABSTRACT FROM PUBLISHER]

We present experimental results obtained from full-waveform measurements of single-event transients (SETs) occurring in the conventional two-input AND and OR gates under focused heavy-ion radiation. Chips with test circuits were fabricated in a 65-nm bulk CMOS technology, and were irradiated in a microbeam facility using 197Au and 48Ca species. The resulting SETs were sensed using a dedicated on-chip analog multiplexer circuit. The obtained position-dependent ion hit responses were analyzed, and the strong evidence of charge-sharing-induced pulse quenching was observed. For SETs that propagated through the inverting stage of AND and OR circuits, a significant degradation of measured SET pulse widths and heights was seen. These observations are in good accordance with earlier published simulation and experimental results based on inverter chains. Test circuits also exhibited distinct SET responses depending on their logic state, making the AND gate a better candidate for exploiting the pulse quenching effect when circuits are placed in a triple well. [ABSTRACT FROM PUBLISHER]

Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed. [ABSTRACT FROM PUBLISHER]

The single-event sensitivity of bulk 40-nm sequential circuits is investigated as a function of temperature and supply voltage. An overall increase in SEU cross section versus temperature is observed at relatively high supply voltages. However, at low supply voltages, there is a threshold temperature beyond which the SEU cross section decreases with further increases in temperature. Single-event transient induced errors in flip-flops also increase versus temperature at relatively high supply voltages and are more sensitive to temperature variation than those caused by single-event upsets. [ABSTRACT FROM PUBLISHER]