Search

This article investigates the single-event effects on 16-nm bulk field-effect transistors (FinFETS) in terms of single-bit upsets and multiple-cell upsets under heavy ion irradiation. These upsets are analyzed and classified according to voltage, linear energy transfer of ions, data patterns, and fail bit patterns. The analysis suggested a characteristic charge collection mechanism attributable to the FinFET structure. Estimation of a unique sensitive area shape based on cross sections is also discussed. [ABSTRACT FROM AUTHOR]

The impact of back-gate bias on the total ionizing dose (TID) response of silicon-on-insulator (SOI) nanowire field-effect transistors (NWFETs) is investigated. The voltage shift induced by TID is studied using different NWFET geometries and as function of the bias applied to the back-gate made of the silicon substrate. Modifications induced on static electrical characteristics, that is, drain current versus gate-to-source voltage ID(VGS) characteristics, are investigated. Experimental results highlight that the bias applied to the back-gate during I−V measurements strongly impacts the NWFET TID response. At 0 V applied to the back-gate, a usual TID behavior is observed. I−V curves are shifted to negative VGS values, which is consistent with the literature. In contrast, two competing mechanisms are shown when negative biases are applied to the back-gate. ID(VGS) curves are first shifted to positive VGS values for low TID before showing a more usual negative TID-induced voltage shifts. This two-step behavior may be attributed to several phenomena. They include either a modification of the net trapped charge sign for several back-gate biases and/or a motion of carriers trapped into the Buried OXide (BOX). The major goal of this article is to identify the mechanism at stake which drives this combined TID/electrostatic behavior. [ABSTRACT FROM AUTHOR]

We evaluate the total-ionizing-dose (TID) responses of InGaAs nMOS fin field-effect transistors (FinFETs) with a modified gate-stack irradiated with 10-keV X-rays under different gate biases. This modified InGaAs nMOS FinFET process shows decreased subthreshold leakage current and increased hysteresis in as-processed devices, and reduced hole trapping in irradiated devices, than first-generation development-stage devices. The reduction in subthreshold leakage current is attributed to changing the buffer layer from GaAs to In0.3Ga0.7As, thereby enhancing the material quality. Both the increased hysteresis in as-processed devices and reduced hole trapping in irradiated devices are attributed primarily to thinning the Al2O3 layer that separates the HfO2 from the InGaAs layers. This facilitates charge exchange with defects at the HfO2/Al2O3 interface and reduces the percentage of radiation-induced holes that are generated in Al2O3 and trapped in HfO2. The removal of a tungsten layer above the TiN gate reduces the interface dose enhancement. [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) response of pMOS nanowire field-effect transistors (NWFETs) is investigated using X-ray irradiations. The TID-induced voltage shift is studied using two NWFET widths and four bias configurations. Both the impact of the geometry and the influence of the bias configuration during irradiation on the radiation-induced trapped charges into the buried oxide are thus addressed. The impact of gate length downsizing on the NWFET’s electrical characteristics in several bias configurations is studied and compared to one of the nMOS NWFETs to state on the mechanisms which leads to their TID response. [ABSTRACT FROM AUTHOR]