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This paper investigates the total ionizing dose response of advanced nonplanar triple-gate transistors with short gate length, as a function of device geometry. Experiments and three-dimensional (3-D) simulations using a radiation dedicated code are used to analyze the buildup of a trapped charge in the buried oxide and its impact on the device electrical characteristics. The behaviors of three prospective nonplanar devices are detailed and compared to the total ionizing dose degradation of a planar fully depleted single-gate architecture. The [OMEGA]-gate FET is shown to be the most tolerant to a 500 krad(Si[O.sub.2]) total dose exposure thanks to the efficient control provided by the lateral gates over the electrostatic potential throughout the Si film and essentially at the Si fin/BOX interface. Index Terms--Fully depleted, multiple-gate transistors, nonplanar architectures, silicon-on-insulator (SOI), total ionizing dose tolerance.

Total ionizing dose effects are investigated for the first time in deca-nanometer fully depleted (FD) silicon-on-insulator (SOI) devices. Charge trapping and the influence of device architecture are investigated in transistors with and without external body contacts. A radiation-induced high current regime is measured in floating body devices, both at high and low drain voltages. The mechanism responsible for the onset of this high current regime is investigated by 2D numerical simulations, and shown to result from the combined effect of short gate length and floating body potential in the intrinsic Si film. Transistors with a doped Si film are less sensitive to the high current regime. The use of external body contact in the device architecture completely stops the onset of high current regime, whatever the device gate length. Index Terms--Fully depleted, NMOS transistors, silicon on insulator, total dose irradiation.

Pseudo-metal-oxide-semiconductor (MOS) silicon-on-insulator (SOI) transistors are used to study the total ionizing dose response of buried oxides. The concentrations of radiation-induced oxide-trap and interface-trap charge are separated using midgap and dual-transistor charge separation analysis techniques. Dual-transistor analysis is shown to be especially well suited for charge separation of pseudo-MOSFETs ([PSI]-MOSFETs) because the electron conduction mode of this simple point-contact device resembles an nMOS transistor, and the hole conduction mode resembles a pMOS transistor. That this is a single device ensures that the dual-transistor assumption of equal oxide-trap charge in otherwise identical n and pMOS transistors is satisfied automatically. Both electron and hole conduction current-voltage (I-V) traces must extrapolate to a common, physically realistic midgap voltage; this is employed as a test for the self-consistency of [PSI]-MOSFET data. Charge separation performed using midgap and dual-transistor analyses show good agreement for the devices employed in this paper. Index Terms--Charge separation, dual transistor method, midgap method, pseudo-MOSFET, SOI transistor.

An analytical model and experimental results are proposed to account for the floating body effects in Silicon-On-Insulator (SOI) MOSFET's. It is shown both theoretically and experimentally that an SOI MOSFET may exhibit simultaneously a negative conductance and a negative transconductance. The evolution of these effects under an X-ray exposure is studied and described in detail.