1. The Associative Memory System Infrastructures for the ATLAS Fast Tracker
- Author
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Hikmat Nasimi, D. Calabro, Stamatios Gkaitatzis, K. Kordas, S. Donati, Andrea Negri, Nicolo Vladi Biesuz, Takashi Kubota, P. Kalaitzidis, Naoki Kimura, Konstantina Mermikli, Dimitrios Sampsonidis, Mauro Dell'Orso, Alberto Annovi, Francesco Crescioli, Vincenzo Greco, P. Giannetti, R. Beccherle, Christos Gentsos, B. Magnin, Calliope Louisa Sotiropoulou, P. Luciano, D. Dimas, Lucian Stefan Ancu, Ioannis Maznas, Federico Bertolucci, M. Piendibene, A. Lanza, Saverio Citraro, Alessandro Iovene, A. Sakellariou, Johanna Gramling, Guido Volpi, Spiridon Nikolaidis, Laboratoire de Physique Nucléaire et de Hautes Énergies (LPNHE (UMR_7585)), and Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Paris Diderot - Paris 7 (UPD7)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS)
- Subjects
Nuclear and High Energy Physics ,Engineering ,parallel processing ,Serial communication ,Integrated circuit design ,computer.software_genre ,7. Clean energy ,01 natural sciences ,030218 nuclear medicine & medical imaging ,03 medical and health sciences ,0302 clinical medicine ,pattern matching (PM) ,Application-specific integrated circuit ,0103 physical sciences ,Electronic engineering ,[PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det] ,Electrical and Electronic Engineering ,trigger: upgrade ,Field-programmable gate array ,Application specific integrated circuits ,field-programmable gate arrays (FPGAs) ,image processing ,trigger circuits ,Nuclear Energy and Engineering ,track data analysis ,010308 nuclear & particles physics ,business.industry ,Firmware ,electronics: communications ,ATLAS ,Content-addressable memory ,Upgrade ,electronics: readout ,integrated circuit: design ,business ,computer ,performance ,Computer hardware ,electronics: design ,VMEbus - Abstract
International audience; The associative memory (AM) system of fast tracker (FTK) processor has been designed for the tracking trigger upgrade to the ATLAS detector at the Conseil Europeen Pour La Recherche Nucleaire large hadron collider. The system performs pattern matching (PM) using the detector hits of particles in the ATLAS silicon tracker. The AM system is the main processing element of FTK and is mainly based on the use of application-specified integrated circuits (ASICs) (AM chips) designed to execute PM with a high degree of parallelism. It finds track candidates at low resolution which become seeds for a full resolution track fitting. The AM system implementation is based on a collection of large 9U Versa Module Europa (VME) boards, named “serial link processors” (AMBSLPs). On these boards, a huge traffic of data is implemented on a network of 900 2-Gb/s serial links. The complete AM-based processor consumes much less power (~50 kW) than its CPU equivalent and its size is much smaller. The AMBSLP has a power consumption of ~250 W and there will be 16 of them in a crate. This results in unusually large power consumption for a VME crate and the need for complex custom infrastructure in order to have sufficient cooling. This paper reports on the design and testing of the infrastructures needed to run and cool the system which will include 16 AMBSLPs in the same crate, the integration of the AMBSLP inside a first FTK slice, the performance of the produced prototypes (both hardware and firmware), as well as their tests in the global FTK integration. This is an important milestone to be satisfied before the FTK production.
- Published
- 2017