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A phase-delay cold-FET pre-distortion linearizer technique is proposed to improve the gain compensation ability compared with the conventional cold-FET pre-distortion linearizer. The gain expansion analysis of the power amplifier (PA) cascading with a pre-distortion linearizer and the comparison with the conventional linearizer and the proposed phase-delay linearizer are provided in this paper. To demonstrate the feasibility of this concept, a single-ended V-band cascode PA with the 90^\circ phase-delay linearizer and a differential K-band common-source PA with the 180^\circ phase-delay linearizer are developed to verify the characteristics. The V-band PA implemented in 90-nm CMOS process exhibits the output 1-dB compression power (OP1~dB) of 13.7 dBm and the power-added efficiency (PAE) at OP1~dB of 14.3%. The K-band PA implemented in 0.18- \mum CMOS process demonstrates 17.5-dBm OP1~dB and 13.6% PAE at OP1~dB. [ABSTRACT FROM AUTHOR]

For the power amplifier (PA) used in code-division multiple-access cellular phones, the supply voltage is switched from around 1.5 to 3.5 V at the boundary transmission power of several decibels higher than 10 dBm using a dc-dc converter to improve operation efficiency. Recently, however, this boundary transmission power is being raised. We applied the second harmonic injection to reduce distortion and maximize the boundary transmission power under low supply voltage. This paper presents the design concept of the PA's load impedance and bias network with second harmonic injection using Volterra-series analysis. We also present a design of the final stage of the PA under low supply voltage and show that the final stage has a drain efficiency of 53% at an output power of 21 dBm. [ABSTRACT FROM AUTHOR]