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In this article, a sparse-Bayesian treatment is proposed to solve the crucial questions posed by power amplifier (PA) and digital predistorter (DPD) modeling. To learn a model, the advanced Bayesian framework includes a group of specific processes that maximize the likelihood of the measured data: regressor pursuit and identification, coefficient estimation, stopping criterion, and regressor deselection. The relevance vector machine (RVM) method is reformulated theoretically to be implemented in complex-valued linear regression. In essence, given an initial set of candidate regressors, the result of this sparse-Bayesian learning approach is the most likely model. Experimental results are provided for the linearization of class AB and class J PAs driven by a 30-MHz fifth-generation new radio signal for a fixed average power, where the evolution of the figures of merit versus the number of active coefficients is examined for the proposed sparse-Bayesian pursuit (SBP) algorithm in comparison to other greedy algorithms. The SBP presents a good performance in terms of linearization capabilities and computational cost. Furthermore, the proposed Bayesian framework enabled the design of a DPD model structure, deselect regressors, and readjust coefficients in a direct learning architecture, demonstrating the robustness to changes in the power level over a 10-dB range. [ABSTRACT FROM AUTHOR]

In this article, we study closed-loop digital predistortion (DPD) systems and associated learning algorithms. Specifically, we propose various low-complexity approaches to estimate and manipulate the inverse of the input data covariance matrix (CM) and combine them with the so-called self-orthogonalized (SO) learning rule. The inherent simplicity of the SO algorithm, combined with the proposed solutions, allows for remarkably reduced complexity in the DPD system while maintaining similar linearization performance compared to other state-of-the-art methods. This is demonstrated with thorough over-the-air (OTA) mmW measurement results at 28 GHz, incorporating a state-of-the-art 64-element active antenna array, and very wide channel bandwidths up to 800 MHz. In addition, complexity analyses are carried out, which together with the measured linearization performance demonstrates favorable performance–complexity tradeoffs in linearizing mmW active array transmitters through the proposed solutions. The techniques can find application in systems where the power amplifier (PA) nonlinearities are time-varying and thus frequent or even constant updating of the DPD is required, good examples being mmW adaptive antenna arrays as well as terminal transmitters in 5G and beyond networks. [ABSTRACT FROM AUTHOR]

Changes in ambient temperature or chip temperature result in variations in the in-phase and quadrature (I/Q) gain and phase imbalance. As a consequence, the overall system performance can be seriously degraded, especially in wideband multi-Gb/s systems, where the I/Q imbalance is highly selective in frequency. Unless appropriately considered, temperature drifts can decrease the image rejection ratio (IRR) of the transmitter. This article presents a novel compensation method for temperature-dependent transmitter I/Q imbalance over the entire temperature range. It consists of a simple predistortion technique that, based on a few factory characterizations of gain and phase imbalance, is able to estimate and correct the I/Q imbalance at any temperature, without interrupting the normal functionality of the system. The proposed method is assessed in a 2-GHz, 64-QAM transceiver implemented with real hardware. The measurements show that the proposed approach is able to keep the IRR greater than 35 dB in the entire bandwidth and an error vector magnitude (EVM) lower than 3% over a temperature range of 70 °C. [ABSTRACT FROM AUTHOR]

This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient’s update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance. [ABSTRACT FROM AUTHOR]

A novel transmitter architecture that uses only envelope modulators is proposed. The complex baseband signal is decomposed into components using a three-coordinate decomposition technique. The individual components are translated to RF using three variable gain amplifiers (VGAs), which act as envelope modulators. The outputs of the VGAs are combined to generate the complex modulated RF signal. The proposed architecture does not have any phase modulator circuit and avoids phase noise and bandwidth expansion issues associated with polar topologies. This architecture avoids the use of any mixers or quadrature up-converters for frequency up-conversion. Accordingly, spurs that are associated with mixer circuits are avoided and, hence, no filtering is needed at the RF output of the transmitter. As RF filters are absent, this architecture offers wider RF bandwidth and would improve the design reconfigurability and integration capability. The signal at the output of the amplitude modulation-based transmitter has distortion due to gain and phase nonlinearity in the VGAs. A new memory polynomial-based modeling approach is used to linearize the transmitter. The performance of the implemented transmitter is evaluated using Long Term Evolution (LTE) signals and the measured error vector magnitude (EVM) and the adjacent channel leakage-power ratio (ACLR) are used to assess the signal quality. The measured EVM of the LTE signal of 1.4 MHz bandwidth, improved from 15% to 0.5% using digital predistortion technique, while the obtained ACLR is 54 dBc. [ABSTRACT FROM PUBLISHER]

A simple and flexible technique for improving the modeling and predistortion of power amplifiers is presented. The technique, which relies on the sparsity assumption for the kernel coefficients of the full Volterra (FV) behavioral model, combines a greedy algorithm for the selection of the active coefficients, a maximum likelihood method for their estimation and an information criterion for determining the best model. The approach has been applied to the design of reduced-parameters FV-based digital predistorters for three power amplifiers driven with orthogonal frequency division multiplexing signals, following the LTE and DVB-T2 standards, and a multichannel wideband code-division multiple access signal. Results show that the proposed linearizers meet the spectral masks and error vector magnitude constraints of the referred standards and provide a reduction better than 45% in the number of parameters, compared to the FV predistorters. [ABSTRACT FROM AUTHOR]

This paper analyzes the effects of load impedance mismatch in power amplifiers which linearity has been enhanced using various digital predistortion (DPD) algorithms. Two different power amplifier architectures are considered: a class AB and a Doherty amplifier and three model structures for the DPD model are compared: memoryless polynomial (MLP), general memory polynomial (GMP) and Kautz-Volterra functions (KV). This paper provides a sensitivity analysis of the linearized amplifiers under load mismatch conditions and reports the performance when dynamic parameter identification for the DPD is used to compensate for the changes in the load impedance. In general, power amplifiers linearity is sensitive to load impedance mismatch. Linearity may degrade as much as 10 dB (in normalized mean square error) according to the magnitude and the phase of the reflection coefficient provided by the load impedance. However, depending on the amplifier design, the sensitivity to load impedance mismatch varies. While the Doherty amplifier studied show significant linearity degradations in the in-band and out-of-band distortions, the out-of-band distortions of the studied class AB were less sensitive to the load impedance mismatch. In adaptive DPD schemes, the performance obtained in the MLP model does not benefit from the updating scheme and the performance achieved is similar to a static case, where no updates are made. This stresses the memory requirements in the predistorter. When employing the GMP and the KV models in an adaptive DPD scheme, they tackle to a larger extent the linearity degradations due to load impedance mismatch. [ABSTRACT FROM AUTHOR]

In this paper, we further develop the concept of a wideband Doherty power-amplifier topology with reconfigurable efficiency. This is done by presenting new theory that - in contrast to previous work - makes it possible to analyze how the performance of the amplifier depends on the input network properties and the choice of gate bias voltages. The utility of the presented theory is demonstrated by the design and characterization of a gallium-nitride monolithic-microwave integrated-circuit amplifier designed in close agreement with the theoretical findings. Continuous-wave (CW) measurements show that the fabricated amplifier provides more than 31% power-added efficiency (PAE) at 9-dB output power back-off over a 5.8-8.8-GHz frequency range, and that the efficiency can be reconfigured as predicted by the presented theory. Modulated measurements - employing digital pre-distortion (DPD) and a 20-MHz signal with 8.5-dB peak-to-average power ratio - show more than 32% average PAE across the same 5.8-8.8-GHz frequency range. Both the CW and the modulated measurements thereby verify the wideband performance predicted by the theory. In addition, modulated measurements at 7.0 GHz without DPD show that the amplifier can provide excellent raw linearity by demonstrating -41.0-dBc adjacent channel power ratio and -34.2-dB normalized mean square error. [ABSTRACT FROM AUTHOR]

A novel generalized two dimensional (2-D) digital predistortion (DPD) architecture for concurrent dual-band transmitters is presented. The proposed architecture is based on simultaneous injection of in-band intermodulation (IM) and cross-modulation (CM) distortion products. A general fundamental-frequency model for concurrent dual-band transmitter is developed theoretically and proofed experimentally. An individual impact of each IM and CM distortion component is theoretically derived and analyzed. It is clearly proven by theoretical analysis and experiments that the proposed predistorter improves the in-band and out-of-band performances of both signals. The simulation and experimental studies are performed using various signal sets. The proposed predistorter does not depend on frequency separation between bands and has low computational complexity in comparison with concurrent dual-band DPD's state-of-the-art. In addition, it is clearly shown in experiments that when using iterative simultaneous injections, a phenomenon known as distortion compensation limit can be reduced. A presence of memory effects and their mitigation in frequency domain for each band of concurrent dual-band transmitter are also demonstrated in experiments. [ABSTRACT FROM AUTHOR]

A new Doherty amplifier configuration with an intrinsically broadband characteristic is presented based on the synthesis of key ideas derived from the analyses of the load modulation concept and the conventional Doherty amplifier. Important building blocks to implement the proposed Doherty amplifier structure are outlined, which include the quasi-lumped quarter-wave transmission line, as well as the Klopfenstein taper for broadband impedance matching. A 90-W GaN broadband Doherty amplifier was designed and fabricated and achieved an average peak output power of 49.9 dBm, an average gain of 15.3 dB, and average peak and 6-dB back-off efficiencies of 67.3% and 60.6%, respectively, from 700 to 1000 MHz (35.3% bandwidth). The amplifier is shown to be highly linearizable when driven with 20-MHz WCDMA and long-term evolution signals, achieving adjacent channel power ratio of better than -48 dBc after digital predistortion. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and implementation of a millimeter-wave (mm-wave) I/Q modulator and determines the impact of I- and Q-channel nonlinearity, PA nonlinearity, and other nonideal circuit implementations on the error vector magnitude (EVM). The modulator is fabricated in 120-nm SiGe BiCMOS process and occupies an area of 5 mm2 . For a 64-QAM constellation at a 42-GHz carrier frequency, the EVM is less than 2.5% at 48-Mbps data rate. The on-chip digital-to-analog conversion resolution is capable of employing digital pre-distortion (DPD) and calibration. An external power amplifier is linearized to improve the EVM with DPD. To the best of the authors' knowledge, this is the lowest EVM reported at these mm-wave frequencies. [ABSTRACT FROM AUTHOR]

The Neural Network (NN) based models are commonly used in power amplifier modeling and predistorter design, and seen as a potential alternative to model and compensate broadband power amplifiers (PAs) having medium- to-strong memory effects along with high-order nonlinearity. In this paper, we propose a novel computationally efficient behavior model based on complex-Chebyshev functional link neural network (CCFLNN) suitable for dynamic modeling of wireless PAs. The CCFLNN exhibits a simpler compact structure than the previously reported NNs and can require less computational burden during the learning process since it uses the complex-valued topology and does not need the hidden layers, which exist in most of the conventional neural-network-based models. The proposed approach utilizes the complex-valued inverse QR-decomposition-based recursive least square algorithm to update the weighting coefficients of the CCFLNN model. The proposed model is comparatively compared with a real-valued focused time-delay NN model and a conventional memory polynomial model with respect to computation complexities and modeling performance. The accurate modeling capacity of the CCFLNN model is demonstrated through a full characteristic (working in the strongly nonlinear region) 170-W class AB amplifier driven by a multicarrier WCDMA signal. Furthermore, the proposed model has been applied for linearizing a real PA in multicarrier application. Results obtained from the measurement clearly show that the proposed digital predistorter can eliminate various intensity in-band and out-of band distortions. [ABSTRACT FROM PUBLISHER]

This paper presents a direct model structure for describing class-D outphasing power amplifiers (PAs) and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths, and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals' phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch. [ABSTRACT FROM PUBLISHER]

A real-time adaptive digital predistortion system (RT-ADPD) for power amplifier linearization is described in this paper, featuring fast closed-loop adaptation to provide robust linearity across quickly shifting power amplifier (PA) operating conditions. The RT-ADPD system requirements, architecture, and its design methodology are analyzed in detail, with particular emphasis on the optimization of the feedback loop convergence speed and stability. A novel, compact algorithm to achieve rapid adaptation of the predistortion lookup tables, without any prior knowledge of the PA distortion characteristics, is introduced. A prototype of the RT-ADPD system is implemented using a field-programmable gate array (FPGA), and it is experimentally exploited to linearize a handset WCDMA PA module. Due to the linearization action, the PA maximum modulated output power is increased by 1.9 dB, to 30.9 dBm, and its power-added efficiency by 9%, to 48.5%, still maintaining a -40-dB ACPR at a 5-MHz offset. In addition, a true closed-loop adaptation ensures excellent PA linearity under load mismatch and other environmental variations. Indeed, ACPR is improved by up to 15 dB, below -47 dB, under 2:1 VSWR at 28 dBm. Remarkably fast adaptation speed is also demonstrated, as adequate signal fidelity is achieved within a \sim\!\! \50-\mu\s time frame. [ABSTRACT FROM AUTHOR]

In this paper, a novel model is proposed for dual-input high efficiency power amplifier (PA) architectures, such as envelope tracking (ET) and varactor-based dynamic load modulation (DLM). Compared to the traditional single-input modeling approach, the proposed model incorporates the baseband supply voltage/load control as an input. This advantage makes the new approach capable to achieve maximized average power-added efficiency (PAE) and minimized output distortion simultaneously. Furthermore, the new approach has shown to be robust towards time misalignment between the RF input and baseband supply voltage/load control signals, and it can be applied with a reduced-bandwidth baseband supply voltage/load control. Experiments have been performed in a varactor-based DLM PA architecture to evaluate the new modeling approach. The results show that it can achieve 9 and 7 dB better performance than the traditional approaches in terms of adjacent channel leakage ratio and normalized mean square error, respectively. At the same time, the average PAE is maximized. Similar results have been achieved with the proposed model even when reduced-bandwidth baseband load control signal is used or time misalignment between the RF and baseband load control input signals exists. Although the new approach is only tested with DLM architecture in this paper, it is very general and can be applied to ET architectures as well. [ABSTRACT FROM AUTHOR]

This paper presents a novel digitally assisted dual-switch envelope amplifier used for wideband high-efficiency envelope-tracking (ET) base-station power amplifiers (PAs). The proposed envelope amplifier comprises two switching buck converters to provide the high-power ET signal to the RF stage and a wideband linear stage to maintain the envelope signal accuracy. The control technique utilizes digital signal processing in conjunction with analog hysteretic feedback to separately control two high-efficiency switchers and thus successfully reduces power consumption of the linear stage, especially for applications requiring high peak-to-average ratio (PAPR) signals. The overall ET system was demonstrated using GaAs high-voltage HBT PAs. For a variety of signals ranging from 6.6- to 9.6-dB PAPR and up to 10-MHz RF bandwidth, the overall system power-added efficiency reached 50%–60%, with a normalized root-mean-square error below 1% and the first adjacent channel leakage power ratio of -\55 dBc after digital predistortion with memory mitigation, at an average output power above 20 W and 10-dB gain. [ABSTRACT FROM AUTHOR]

In this paper, a detailed linearization procedure for dynamic load modulation (DLM) transmitter architectures is proposed for the first time. Compared with the conventional single-input/single-output digital predistortion (DPD) approach used with traditional power amplifiers (PAs), the proposed linearization scheme is based on a regular memory DPD in combination with an efficiency-optimized static one-to-two mapping inverse model, which constructs the predistorted input signals to the DLM transmitter. The time-alignment issue, which is very important to this dual-input architecture, is also considered. The proposed technique is demonstrated by a 1-GHz 10-W LDMOS PA that employs a varactor-based tunable matching network. A normalized mean square error of -35 dB, and adjacent channel leakage ratio of -43 dBc is achieved, with an average power-added efficiency of 53% for a single-carrier WCDMA signal with 7-dB peak-to-average ratio. Finally, it is shown that the time-alignment sensitivity is relaxed when the proposed linearization scheme is used. This means that the overall complexity of the transmitter implementation can be reduced. [ABSTRACT FROM AUTHOR]

A novel approach for power amplifiers static non-linearity characterization in the presence of memory effects is presented. A subsampling technique is used to reduce the bandwidth of the test signal without changing the waveform characteristics. This cancels the memory effects of the amplifier without affecting its static behavior. Memoryless AM/AM and AM/PM characteristics are measured as a function of the carrier frequency. This points out the contribution of the frequency dependency of the amplifier's static nonlinearity to its behavior under wideband signal drive. A memoryless post-compensation technique is then introduced to accurately assess the performance of several behavioral models. In fact, it is demonstrated that direct comparison of the measured output of the device-under-test with the estimated output does not provide reliable assessment of the model performance. Conversely, memoryless post-compensation efficiently differentiates the performance of these models. To provide a comprehensive approach for model validation and prototype performance evaluation, memory effects intensity metrics are introduced. These metrics are applied to evaluate the memory effects present in a 300-W peak power Doherty amplifier driven by various multicarrier wideband code division multiple access signals. [ABSTRACT FROM AUTHOR]

A comparison of envelope elimination and restoration (EER) and envelope tracking (ET) is discussed and a ‘hybrid’ wideband EER power amplifier (PA) for the WLAN 802.11g system is proposed. A 60% efficiency (the output envelope signal power/input dc power) DC-20-MHz wideband envelope amplifier is designed for wideband EER and wideband ET (WBET) applications. A design method is developed to optimize the efficiency of the envelope amplifier for a given peak-to-average ratio and average slew rate of the envelope signal. An experimental ‘hybrid’ Class-E EER system shows an overall efficiency (modulated RF output power/envelope amplifier dc input power) of 36% and power-added efficiency (the modulated RF output power/envelope amplifier dc input power plus RF input power) of 28% for a WLAN 802.11g signal at 19-dBm (80 mW) output power at 2.4 GHz. Digital predistortion, time alignment, and memory effect mitigation are implemented. The measured 3 % error vector magnitude exceeds the 802.11g specification for 5% for a 54-Mb/s modulation signal. [ABSTRACT FROM AUTHOR]

We present in this paper an advanced adaptive base-band/RF predistorter that integrates the concept of the software-defined radio technology into the power-amplifier (PA) linearization area. The linearizer performs an instantaneous characterization of the PA, using two digital receivers, in order to supply its instantaneous AM-AM and AM-PM curves. It then determines an inverse function that represents the best fit to the reciprocal of the PA behavior. Code-division multiple-access and third-generation standard signals applying different stress level on the PA are used to evaluate the performance of the linearizer. The system is validated using digital signal processing/RF co-simulation for a typical 44-dBm class-AB PA. To estimate the performance of the linearizer under realistic condition, experimental results have been carried out in open-loop condition, supported by a software-instruments connectivity, for a 20-W class-AB PA operating at 1.96 GHz. Results for different cases of standards signals reveal a significant reduction, in the order of 5 dB, in effective output power backoff. [ABSTRACT FROM AUTHOR]