Search

In high-speed analog-to-digital converters (ADCs), two main factors contribute to high power consumption. The first is the super linear relationship with the sampling rate; i.e., by doubling the sampling rate, the power consumption more than doubles. The second factor arises from the consumption of analog circuitry responsible to mitigate the jitter noise. By employing a multichannel sampling system, one can achieve high sampling rates by incorporating multiple low sampling-rate channels, which results in a linear scaling of power consumption with the number of channels. The main drawback of this system is the timing mismatch between the sampling channels. In this paper, we intend to jointly compensate the jitter noise and the timing mismatch between the channels using statistical methods. We first approximate the acquisition system and derive a stochastic model. Then, we propose an iterative maximum likelihood algorithm to estimate the parameters of the input signal. We further evaluate the Cramér-Rao lower bound (CRLB) for the estimation error to examine the proposed algorithm. Simulation results indicate that our algorithm is capable of closely following the CRLB curve for reasonable values of jitter noise and a wide range of timing mismatch errors. Moreover, it is shown that the mismatch-compensated multichannel sampling system performs almost equivalently to a single-channel high rate sampler without having its shortcomings. [ABSTRACT FROM AUTHOR]

Nonsynchronous sampling conditions are the source of leakage errors in measurements based on digital signal processing. The optimal method to avoid such errors is to generate a synchronous sampling clock, whenever the input signal shows enough period stability to allow this. Such method, however, does not yield a straightforward evaluation of the input signal frequency, which is required in several applications. This paper proposes a modified synchronous clock generator that together with a modified frequency interpolation algorithm provides an accurate measurement of the input signal frequency when the only available information about the sampling clock is a given integer multiple of the input signal fundamental frequency. [ABSTRACT FROM AUTHOR]