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We investigated the SiN/gallium nitride (GaN) interface properties formed by the microwave-excited plasma-enhanced chemical vapor deposition (PECVD) with SiH4/N2/H2 gases. The interface and insulating properties of SiN films on GaN formed by the microwave-excited PECVD strongly depend on SiH4 flow rate. Although the interface trap density is lower than $10^{11}$ cm $^{\mathrm {-2}}$ eV $^{\mathrm {-1}}$ at the relatively high SiH4 flow rate of 1 sccm, the breakdown electric field is very low ( $\sim 1$ MV/cm). Using the SiH4 plasma pretreatment before the stoichiometric SiN deposition, both low interface trap density and high breakdown voltage greater than 2 MV/cm are obtained. In this case, the clearly ordered Ga bonding near the SiN/GaN interface is estimated by an electron energy loss spectroscopy. The formation of SiN film on GaN using the microwave-excited PECVD is a very useful technique for the high-quality interface properties.

This paper presents, for the first time, the successful integration of three rapid, low-cost, high-throughput technologies for silicon solar cell fabrication, namely: rapid thermal processing (RTP) for simultaneous diffusion of a phosphorus emitter and aluminum back surface field; screen printing (SP) for the front grid contact; and low-temperature plasma-enhanced chemical vapor deposition (PECVD) of SiN for antireflection coating and surface passivation. This combination has resulted in 4 cm/sup 2/ cells with efficiencies of 16.3% and 15.9% on 2 /spl Omega/-cm FZ and Cz, respectively, as well as 15.4% efficient, 25-cm/sup 2/ FZ cells. Despite the respectable RTP/SP/PECVD efficiencies, cells formed by conventional furnace processing and photolithography (CFP/PL) give /spl sim/2% (absolute) greater efficiencies. Through in-depth modeling and characterization, this efficiency difference is quantified on the basis of emitter design and front surface passivation, grid shading, and quality of contacts. Detailed analysis reveals that the difference is primarily due to the requirements of screen printing and not RTP.

Details of a large-area-compatible sub-600 °C process for the fabrication of high mobility field-effect transistors on single crystalline silicon are presented. It is shown that lift-off and solid-phase-epitaxy (SPE) can be used in conjunction with plasma enhanced chemical vapor deposition (PECVD) to create MOSFET transistors with mobilities comparable to other high-performance techniques. Furthermore, use of an amorphous silicon/silicon oxynitride (SiO x N y ) sacrificial bilayer is shown to make the process capable of self-aligned silicidation. The topography of the deposition is studied using cross-sectional scanning electron microscopy (SEM). It is shown that a successful lift-off can be achieved through the proper design of the sacrificial bilayer despite the high degree of step coverage generally exhibited by PECVD films. Cross-sectional transmission electron microscopy (TEM) is used to reveal the microstructure of the epitaxy and silicidation. Current-voltage characteristics of the fabricated transistors are presented and the field effect mobility of electrons on the fabricated devices is reported. The developed process is particularly useful in applications where high mobility transistors need to be built on silicon/nonsilicon hybrid platforms that exclude high processing temperatures.

Amorphous indium gallium zinc oxide (IGZO) deposited by plasma-enhanced atomic layer deposition (PEALD) thin-film transistors (TFTs) was fabricated using SiO2 gate insulators synthesized via plasma-enhanced chemical vapor deposition (PECVD, device A) or PEALD (device B). The electrical performance of B devices was higher than that of device A. The mobilities of A and B devices were 19.39 and 21.11 cm2/Vs, and the subthreshold slopes were 0.25 and 0.22 V /decade, respectively. In addition, the device reliability of A devices shows an abnormal threshold voltage ( ${V}_{\text {th}}$ ) shift of –1.25 V under positive bias temperature stress (PBTS), caused by hydrogen diffusion from the gate insulator to the channel region near the source/drain electrode. However, B devices had a normal ${V}_{\text {th}}$ shift of +2.87 V. X-ray photoelectron spectroscopy (XPS) and Fourier-transform infrared spectroscopy (FT-IR) results showed that PECVD SiO2 has a large amount of hydrogen bonding, such as Si-OH, compared to PEALD SiO2. Rutherford backscattering spectroscopy (RBS) and elastic recoil detection (ERD) measurement results confirmed that the hydrogen content of PECVD SiO2 was 2.24%, whereas that of PEALD SiO2 was lower at 1.45%.

Interface trapping is one of the most notorious effects that limit device performance in GaN-based MIS high electron mobility transistors (MISHEMTs). In this paper, we present a comprehensive study on interface traps in AlGaN/GaN MISHEMTs using low pressure chemical vapor deposition SiNx as gate dielectric. We combined the trapping analysis in MIS diodes and actual MISHEMTs to estimate the interface trap state densities ( $\text{D}_{\mathrm {it}})$ and their distributions in the device, and to investigate their influence on device electrical properties. Two types of interface traps with different emission time constants, designated as “slow” and “fast” traps, were identified and characterized by means of pulse-mode current-voltage measurements and a frequency dependent conductance method. It was found that “fast” traps located in the device access region could be effectively restrained by passivation using plasma enhanced chemical vapor deposition SiNx. However, “slow” traps, no matter whether located beneath the metal gate or in the access region, were less influenced by passivation. Due to the strong interference of traps in the access region, $\text{D}_{\mathrm {it}}$ extraction using the conventional conductance method was not accurate for the lateral GaN-based MIS diodes. A modified small-signal equivalent circuit that includes the impedance of traps in the access region is proposed. Proper passivation for the device access region is essential when using the conductance method for GaN-based MIS devices.

We have developed 0.1- $\mu \text{m}$ gate-length InAlN/GaN high electron-mobility transistors (HEMTs) for millimeter-wave (MMW) power applications, particularly at 71–76 and 81–86 GHz bands. The impacts of depth and width of the gate recess groove on electrical performance have been analyzed and compared. Competing passivation technologies, atomic layer deposition (ALD) aluminum oxide (Al2O3) and plasma-enhanced chemical vapor deposition (PECVD) SiN, have also been assessed in terms of dc, pulsed- $IV$ , and high-frequency characteristics. It has been found that while PECVD SiN-passivated HEMTs and the monolithic microwave integrated circuits slightly underperform their ALD Al2O3-passivated counterparts, their MMW power performance can be further boosted with the gate recess due to the improved aspect ratio and scaling characteristics. When biased at a drain voltage of 10 V, a first-pass two-stage power amplifier design based on recessed PECVD SiN-passivated 0.1- $\mu \text{m}$ depletion-mode devices has demonstrated an output power of 1.63 W with a 15% power-added efficiency at 86 GHz.

The optical emission spectrometer (OES) is an effective experimental tool for monitoring plasma states and the composition of gases during the growth of silicon thin films by plasma-enhanced chemical vapor deposition. In this paper, hydrogenated amorphous silicon (a-Si) (a-Si:H) and microcrystalline silicon (μc-Si) thin films have been deposited in a parallel-plate radio frequency (RF) plasma reactor using silane and hydrogen gas mixtures. The plasma emission atmosphere was recorded using an OES system during the growth of the Si thin films. The plasma was simultaneously analyzed during the process using an OES method to study the correlation between growth rate and microstructure of the films. In the deposition, the emitted species (SiH*, Si*, and H*) were analyzed. The OES analysis supported a chemisorption-based deposition model of the growth mechanism. The effects of RF power, electron-to-substrate distance, and H2 dilution of the emission intensities of excited SiH, Si, and H on the growth rate and microstructures of the film were studied. Finally, single-junction a-Si:H and μc-Si solar cells were obtained with initial aperture area efficiencies of 9.71% and 6.36%, respectively. A tandem a-Si/μc-Si cell was also realized with an efficiency of 12.3%.

A dense plasma enhanced chemical vapor deposition (PECVD) SiCOH film and a porous ultralow-κ (pULK) film have been investigated by means of the Fourier transform infrared spectroscopy. Structural differences between both materials have been found in particular in the amount of silanol groups and in the location and shape of the Si-O-Si stretching vibration band. Furthermore, moisturized samples of these materials have been investigated in situ during outgassing in rough vacuum. It has been observed that the pULK film contains only about 25% of the water amount found in the dense SiCOH film in saturation at 80% relative humidity and room temperature. A comparison of the water-related species in the investigated dielectric films with a liquid water spectrum identified hydrogen-bonded water-silanol groups in both materials and hydrogen-bonded water-water groups in the pULK film. During the outgassing process, no indication of shrinking or other structural changes were found, except for a shift in the silanol-associated vibration band to slightly higher wavenumbers. The achieved results are in good agreement to previous electrical characterization of both dielectric films.

In this paper, we report on the fabrication of flexible amorphous-silicon (a-Si) thin-film solar cells on a parylene template carried by a glass plate without any adhesive. The a-Si thin-film solar cells could be separated directly from the glass carrier after a process temperature of up to 200°C. The a-Si and parylene films were deposited using high-frequency plasma-enhanced chemical vapor deposition and a parylene reactor. The parylene-coated glass plate was treated with thermal annealing and Ar, N2, or O2 plasma. Moreover, SiNx and/or SiOx films were used as barrier layers between the transparent conductive oxide and parylene films. Details of different gas plasmas and barrier effects were investigated in terms of surface morphologies and solar cell characteristics. The a-Si thin-film solar cell on a parylene template with an open-circuit voltage of 0.74 V, a short-circuit current density of 15.69 mA/cm2, a fill factor of 54.98%, and a conversion efficiency of 5.78 % could be obtained. After the 10-mm-radius bending test for 5000 times, the a-Si thin-film solar cells still exhibited a conversion efficiency of 4.94%. These results indicated that a-Si thin-film solar cells on parylene templates have high potential for flexible photovoltaic applications.

We have demonstrated a back surface process for back-illuminated high-purity p-channel charge-coupled devices (CCDs), enabling broadband coverage from the ultraviolet to near infrared (NIR). The process consists of the formation of a delta layer followed by a double layer antireflection (AR) coating. The process is performed below 450degC and is applied to fully fabricated CCDs with aluminum metallization. The delta doping process was demonstrated on 1 k times 1 k and 2 k times 4 k CCDs, which were found to exhibit low dark current and near reflection-limited quantum efficiency. Two broadband AR coatings were developed to cover the UV-visible and visible-NIR bands. These coatings consist of a double layer of SixNy and SiOx deposited by plasma enhanced chemical vapor deposition onto the back surface of a delta doped CCD. The thicknesses of the coating layers are adjusted for the desired bandpass.

Plasma-enhanced chemical vapor deposition grown silicon nitride gate insulator with high refractive index of 2.39 was employed as the source of hydrogen to hydrogenate zinc oxide (ZnO) thin-film transistors (TFTs) with bottom-gate configuration. The hydrogenated TFTs exhibited a field-effect mobility of 7.8 cm2/Vmiddots, an on/off current ratio of 106, and a subthreshold slope of 1.2 V/dec. In comparison, TFTs using silicon nitrides with lower refractive indices of 2.26, 1.92, and 1.80 showed relatively poor performance. Dynamic secondary ion mass spectroscopy study showed that the amount of hydrogen present in the ZnO TFT structures using high refractive index silicon nitride gate dielectric is higher than that in the TFT samples using low-refractive index silicon nitride, which indicate the evidence of hydrogenation of ZnO TFTs by high refractive index silicon nitride gate dielectric. The enhanced performance of the hydrogenated TFTs is attributed to the passivation of ZnO/dielectric interface states and doping of the channel by hydrogenation effect.

Thin-film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) made by plasma-enhanced chemical vapor deposition have higher electron and hole field-effect mobilities than their amorphous counterparts. However, as the intrinsic carrier mobilities are raised, the effective carrier mobilities easily can become limited by the source/drain contact resistance. To evaluate the contact resistance, the nc-Si:H TFTs are made with a range of channel lengths. The TFTs are fabricated in a staggered top-gate bottom source/drain geometry. Both the intrinsic and the - or -doped nc-Si:H source/drain layers are deposited at 80-MHz excitation frequency at a substrate temperature of 150 . Transmission electron microscopy of the TFT cross section indicates that crystallites of doped nc-Si:H nucleate on top of the Cr source/drain contacts. As the film thickness increases, the crystallites coalesce, and the leaf-shaped crystal grains extend through the doped layer to the channel i layer. The contact resistance is estimated by measuring IDS for several channel lengths at fixed gate and drain voltages. The results show that the contact resistance depends on the gate voltage and that the source/drain current of these TFTs at VDS = 10 V becomes limited by the contact resistance when the channel length is less than 10 mum for n-channel and less than 25 mum for p-channel.

SiGe/Si heterojunction infrared Schottky-barrier photodetectors (PDs) with different thicknesses (30-60 nm) of amorphous silicon (a-Si:H) cap layers were successfully fabricated. The SiGe and a-Si:H layers were deposited by using ultrahigh-vacuum chemical vapor deposition and plasma-enhanced chemical vapor deposition systems, respectively. In the fabricated PDs, it was observed that the a-Si:H cap layer can effectively suppress a dark current and that the thicker a-Si:H cap can obtain lower dark current. The lowest dark current was observed in the 60-nm a-Si:H capped PDs. When compared with a capless a-Si:H device, the dark current in the 60-nm a-Si:H capped PD was reduced by a magnitude of 317 at 4-V reverse-bias voltage. However, by increasing the a-Si:H thickness, the photocurrent was reduced. Therefore, a compromise in a-Si:H thickness should be chosen. We discovered that the photo-to-dark-current ratio was enhanced by a factor of 850 for 30-nm a-Si:H capped PDs as compared to that of capless a-Si:H devices. Thus, a PD with a higher noise-rejection ability was achieved by merely inserting a thin a-Si:H layer. Possible mechanisms are discussed in detail by the use of spectrum and band diagrams.

We report the fabrication and characterization of bottom-gate and top-gate nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) with amorphous-silicon nitride (a-SiNx:H) as the gate dielectric. The devices were fabricated using standard 13.56-MHz plasma-enhanced chemical vapor deposition at 240 degC. Here, the same 80-nm nc-Si:H channel, 300-nm a-SiNx:H gate dielectric, and 60-nm n+ nc-Si:H ohmic contact layers were used in both TFT structures. We analyzed the effects of gate configuration on TFT performance and, in particular, the electrical stability. The stability tests were carried out at a gate bias stress in the range from 20 to 40 V. The nc-Si:H TFTs demonstrated much better threshold-voltage (VT ) stability compared with the amorphous-silicon (a-Si:H) counterparts, offering great promise for applications in active-matrix organic light-emitting diode (AMOLED) displays

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.

The authors have studied higher dark-current temperature dependence in a trench-electrode Si-based metal-semiconductor-metal (MSM) photodetector which has a hydrogenated intrinsic amorphous silicon (i-a-Si:H) dark-current suppression layer. The poor dark-current temperature-dependence performance could be improved significantly by reducing the number of trap states in the depletion region of the reverse-biased crystalline/amorphous Si heterojunction. To reduce the trap states, a modified plasma-enhanced chemical vapor deposition (PECVD) system, which reduced the ion bombardment on the Si substrate, was employed to deposit an i-a-Si:H layer. Moreover, since fewer trap states in a photodetector will result in a degradation of the fall time of the temporal response of the device, a Ti electrode, which has a lower Schottky barrier height (0.62 eV) than that (0.84 eV) of the previous Cr electrode used with i-a-Si:H, was employed for compensation. The device obtained exhibited very good dark-current stability and temporal response. The dark current only increased from 6 to 34 nA, when the operating temperature was increased from room temperature (R. T.) to 57/spl deg/C, much lower than that of the previously reported 3-V bias voltage one (from 22 to 209 nA). Device responsivity and quantum efficiency also showed obvious improvement, both at R. T. (0.192 A/W and 0.29) and 57/spl deg/C (0.213 A/W and 0.32, respectively) and were higher than those previously reported (0.174 A/W and 0.26, at 57/spl deg/C).

The beneficial effects of sulfur passivation of gallium arsenide (GaAs) surface by (NH/sub 4/)/sub 2/S/sub x/ chemical treatment and by hydrogenation of the insulator-GaAs interface using the plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride gate dielectric film as the source of hydrogen are illustrated by fabricating Al/PECVD silicon nitride/n-GaAs MIS capacitors and metal insulator semiconductor field effect transistors (MISFET). Post metallization annealing (PMA) at temperatures in the range 450-550/spl deg/C is shown to be the key process for achieving midgap interface state density below 10/sup 11//cm/sup 2//eV and maximum incremental transconductance, which is about 75% of the theoretical maximum limit. MIS capacitors are fabricated on (NH/sub 4/)/sub 2/S/sub x/ treated GaAs substrate using gate dielectrics such as PECVD SiO/sub 2/ and silicon oxynitride to demonstrate that the PMA is less effective with these dielectrics because of their lower hydrogen content. The small signal AC transconductance, g/sub ms/ measurements on MISFETs fabricated using silicon nitride, have shown that the low-frequency degradation of g/sub ms/ is almost absent in the devices fabricated on (NH/sub 4/)/sub 2/S/sub x/-treated GaAs substrates and subjected to PMA. The drain current stability in these devices is demonstrated to be excellent, with an initial drift of only 2% of the starting value. The dual role of silicon nitride layer, namely, protection against loss of sulfur and an excellent source of hydrogen for additional surface passivation along with sulfur is demonstrated by comparing the transconductance of MISFETs fabricated on GaAs substrates annealed without the nitride cap after the (NH/sub 4/)/sub 2/S/sub x/ treatment.

In this paper, a comprehensive study on the effect of plasma-enhanced chemical-vapor-deposited SiN surface passivation on the bias-dependent small-signal equivalent-circuit elements is carried out for AlGaN/GaN high-electron mobility transistors on a high-resistivity silicon substrate. The direct-current and small-signal performance of the device was found to be improved by surface passivation. The small-signal equivalent-circuit parameters at various gate and drain biases were extracted, and the physical mechanisms of their bias-dependent behaviors before and after passivation are discussed in detail.

Conventionally directionally solidified (DS) and silicon film (SF) polycrystalline silicon solar cells are fabricated using gettering and low temperature plasma enhanced chemical vapor deposition (PECVD) passivation. Thin layer (/spl sim/10 nm) of PECVD SiO/sub 2/ is used to passivate the emitter of the solar cell, while direct hydrogen rf plasma and PECVD silicon nitride (Si/sub 3/N/sub 4/) are implemented to provide emitter and bulk passivation. It is found in this work that hydrogen rf plasma can significantly improve the solar cell blue and long wavelength responses when it is performed through a thin layer of PECVD Si/sub 3/N/sub 4/. High efficiency DS and SF polycrystalline silicon solar cells have been achieved using a simple solar cell process with uniform emitter, Al/POCl/sub 3/ gettering, hydrogen rf plasma/PECVD Si/sub 3/N/sub 4/ and PECVD SiO/sub 2/ passivation. On the other hand, a comprehensive experimental study of the characteristics of the PECVD Si/sub 3/N/sub 4/ layer and its role in improving the efficiency of polycrystalline silicon solar cells is carried out in this paper. For the polycrystalline silicon used in this investigation, it is found that the PECVD Si/sub 3/N/sub 4/ layer doesn't provide a sufficient cap for the out diffusion of hydrogen at temperatures higher than 500/spl deg/C. Low temperature (/spl les/400/spl deg/C) annealing of the PECVD Si/sub 3/N/sub 4/ provides efficient hydrogen bulk passivation, while higher temperature annealing relaxes the deposition induced stress and improves mainly the short wavelength (blue) response of the solar cells.

We have studied the electron emission characteristics of Mo field emitter arrays (FEAs) using a diamond-like carbon (DLC) film deposited by a layer-by-layer technique using plasma enhanced chemical vapor deposition. The turn-on voltage was lowered from 55 to 30 V by a 20 nm thick hydrogen-free DLC coating and maximum emission current was increased from 166 to 831 /spl mu/A. Also the gate voltage required to get the anode current of 0.1 (/spl mu/A/emitter) decreases from 77 to 48 V. Furthermore, the emission current from DLC coated Mo FEAs is more stable than that of noncoated Mo FEAs.

a-SiC:H p-i-n thin-film LED's (TFLED's) containing a single graded-gap p-i-n junction (SG) or double graded-gap p-i-n and i-n junctions (DG) have been postulated and fabricated successfully on indium-tin-oxide (ITO)-coated glass substrates, with a plasma-enhanced chemical vapor deposition (PECVD) system. Some important characteristics and related physics of these two types of TFLED's are presented and discussed. At an injection current density (J) of 600 mA/cm/sup 2/, the brightness (B) of the SG and DG TFLED's obtained were 30 and 207 cd/m/sup 2/, respectively. This significant improvement of brightness, as compared to those of the previously reported TFLED's with a highest brightness of 20 cd/m/sup 2/, could be ascribed to the reduced interface states with the graded-gap junctions, lower contact resistance between ITO and the p-layer due to plasma treatment of ITO prior to p-layer deposition, post metallization annealing of thermally evaporated Al on n-layer, and higher optical gaps (E/sub opt/'s) of the doped layers employed. The slopes of the nearly linear B-J relationships show a diode factor very close to unity for the fabricated SG and DG TFLED's. This implies that the electroluminescence (EL) mechanism of these TFLED's might be a tail-to-tail-state recombination. In addition, the conduction currents of these TFLED's are almost temperature dependent, and that of the DG TFLED might consist of an ohmic current and a space-charge-limited current (SCLC) within the lower and higher applied-bias regions, respectively.

Silicon nitride (SiN/sub x/) films deposited by plasma enhanced chemical vapor deposition (PECVD) contain large amount of atomic hydrogen which can be driven into bulk silicon by post-PECVD anneal. The objective of this paper is to understand and quantify the effects of the anneal on multicrystalline silicon (mc-Si) solar cells. Detailed cell analysis and model calculations are performed to assess the impact of the anneal on mc-Si cells. Simple n/sup +/-p-p/sup +/ solar cells with PECVD SiN/sub x//SiO/sub 2/ antireflection (AR) coating are annealed in the temperature range of 350/spl deg/C to 700/spl deg/C. The efficiency of the cells made on EFG silicon increases by 45% due to the AR coating and then additional 25% due to the anneal. A trade off between short and long wavelength response is found during the anneal. Low temperature anneal increases the short wavelength response, while high temperature anneal improves the long wavelength response at the expense of the short wavelength response. It is shown that the increase in short wavelength response is due to improved surface passivation, and the decrease in short wavelength response after high temperature anneals is the result of the increase in short wavelength absorption in the SiN/sub x/ film. Higher quality HEM silicon cells do not show appreciable increase in the long wavelength response at higher anneal temperatures. Thus post-PECVD low temperature anneal helps all mc-Si cells, but the effect of high temperature anneal is material specific. Cells made from materials which do not respond to hydrogenation can degrade at high temperature anneal.