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The silicon-controlled rectifier (SCR) has been reported to protect CMOS integrated circuits (ICs), due to high ESD robustness within a small silicon area. However, the holding voltage (Vh) of the SCR device was too low to suffer the latch-up issue. Thus, the Vh value of the SCR device must be improved to be greater than the circuit operating voltage for safe applications. In this work, the Schottky-embedded modified lateral SCR (SMLSCR) with high holding voltage for ESD protection was proposed and verified in a 0.18-μm 1.8-V/3.3-V CMOS process. By using the Schottky barrier junction, the Vh value of the SCR device can be improved by the reverse-bias Schottky barrier diode (SBD) that is embedded into the SCR device structure. Among those experimental results on the SMLSCR devices with split layout parameters in the silicon test chip, the SMLSCR device without P+ guard ring has the best second breakdown current (It2) of 3.1 A and a high Vh value of 9.7 V. [ABSTRACT FROM AUTHOR]

This article discusses the robustness of field-plate-assisted reduced surface field effect (RESURF) DMOS designs to time-dependent latch-up within a single dielectrically isolated device. This work individually characterizes the dopant defined parasitic bipolar parallel to all MOS and uniquely describes the existence of another parasitic bipolar of opposite polarity through the generation of a backgate current as a result of weak impact ionization. These two NPN and PNP bipolar devices in a single DMOS device complete the latch-up mechanism once the product of their gains is greater than one. The characterized time-dependent nature of the increasing backgate current is accounted for by oxide charge trapping in the extended drain region, where measurements of this mechanism over a broad range of application and manufacturing variables enable a mathematical model for the time to failure to be described. Finally, the advantage of analyzing DMOS latch-up robustness in the context of individual parasitic NPN and PNP bipolar devices is shown by its ability to isolate out the separate variables feeding into each bipolar to implement robust solutions. [ABSTRACT FROM AUTHOR]

A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- $\mu \text{m}$ 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge (ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input–output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET’s to the power rails (${V}_{\textsf {DD}}$ or ${V}_{\textsf {SS}}$). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells. [ABSTRACT FROM AUTHOR]

This paper proposes a new concept of Schottky contact insulated-gate bipolar transistor (SC-IGBT), which uses a top surface Schottky contact to the p-base as a hole barrier to enhance the conductivity modulation effect. TCAD simulation shows that the SC-IGBT offers a saturation voltage decrease of 19% or turn-OFF loss reduction of 46% when compared with a conventional field-stop IGBT. Furthermore, it potentially offers an alternative method of fabricating injection enhancement IGBTs, which is simpler than the existing buried n-type layer or narrow mesa trench structures. [ABSTRACT FROM AUTHOR]

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 A/cm^2. The latch-up current density is 1100 A/cm^2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A/cm^2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. [ABSTRACT FROM PUBLISHER]