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The degradations of electrical parameters for silicon carbide power MOSFETs under repetitive short-circuit (SC) stress are investigated in detail in this paper. It demonstrates that the generation of negative charges along the gate–oxide interface of the channel region is the dominant degradation mechanism, which results in the increase in the threshold voltage (${V}_{\text {th}}$) and the rise of ON-state resistance (${R}_{\text {dson}}$) under low gate voltage bias condition. Furthermore, degradations of dynamic characteristics including gate charge (${Q}_{\text {g}}$) and switching behaviors of the device after the repetitive SC stress are extracted and analyzed for the first time. It illustrates that the increased ${V}_{\text {th}}$ contributes to the rise of the Miller plateau voltage (${V}_{\text {gp}}$), which further leads to the increase in gate–source charge (${Q}_{\text {gs}}$). Meanwhile, the increase in the turn-ON time and the reduction of turn-OFF time are observed, which are also resulted from the positive shifts of ${V}_{\text {th}}$ and ${V}_{\text {gp}}$ , leading to the rise of turn-ON switching energy (${E}_{{ \text {on}}}$) and the decline of turn-OFF switching energy (${E}_{\text {off}}$), respectively. [ABSTRACT FROM AUTHOR]

In this paper, the electrical parameter degradations of high-voltage 4H-SiC MOSFETs under repetitive unclamped-inductive-switching (UIS) stresses were investigated experimentally. The holes injection and trapping into the gate oxide above the JFET region is identified to be the main degradation mechanism, resulting in the increase of OFF-state drain–source leakage current ( I\mathrm {DSS}) and the decrease of ON-state resistance ( R\mathrm {dson}) . However, during the repetitive UIS stresses, there is not obvious degradation observed for the threshold voltage ( V\mathrm {th}) of the device. Moreover, three improved SiC MOSFETs structures, one with step gate oxide above the JFET region, one with step p-body region, and another one with floated shallow p-well in the middle of JFET region, were proposed to reduce the degradations under the repetitive UIS stresses. [ABSTRACT FROM AUTHOR]

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional Vg -accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 ^\circC ; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev , when neutral, lift well above Ev after charging, and return below Ev following neutralization. [ABSTRACT FROM PUBLISHER]