Search

In this work, we report atomic-layer-deposited (ALD) based all-oxide transistors toward vertically stacked high-density logic and memory for 3-D integration. This structure utilizes thick degenerated ALD In2O3 as the conducting gate, and ALD In2O3 thin film itself serves as source/drain contacts to the ALD In2O3 channel without metal contacts and gate formation. The all-oxide field-effect transistors (AOFETs) not only survived under high-temperature annealing over $400~^{\circ }$ C but also gained a boosted on-/off-ratio over $10^{{7}}$ with subthreshold swing (SS) close to 60 mV/dec at room temperature. AOFETs present high uniformity and very robust reliability with a threshold voltage instability ( $\boldsymbol {\Delta } {V}_{\text {TH}}\text {)}$ of −5 and −50 mV under positive bias stress (PBS) and negative bias stress (NBS) tests for $10^{{4}}$ s. The vertical AOFETs (V-AOFETs) demonstrate good gate modulation from sidewall In2O3 with thickness as well as gate length ( ${T}_{\text {IO,{g}}}\text {)}$ of 10 nm, achieving on-/off-ratio over $10^{{5}}$ and maximum current ( ${I}_{\max }\text {)}$ over $160~\boldsymbol {\mu } $ A/ $\boldsymbol {\mu } $ m. Vertical all-oxide ferroelectric FETs (V-AO-FeFETs) show a memory window (MW) of 1.85 V, with endurance and retention extended to $10^{{12}}$ cycles and ten years at room temperature, respectively. These findings illustrate that the vertical-channel all-oxide devices based on ALD oxide semiconductors (OS) are promising candidates for future high-density logic and memory applications in 3-D integration.

As transistor dimensions reach the 3-nm node, interface and surface engineering emerges as critical considerations. Challenges introduced by reduced conductivity and mobility due to surface depletion significantly impact thickness scaling and contact performance. In this work, we report the surface accumulation in atomic layer deposition (ALD) grown In2O3 thin-film transistors (TFTs). The negative Schottky barrier enables an ultralow metal-to-semiconductor contact resistance of ${R}_{c} ={23.4} \Omega \, \mu \text { m}$ at electron charge density ${n}_{\text {2D}}={5.0} \times {{10}}^{{13}} \text { cm}^{-{2}}$ in a nanometer ultrathin In2O3 channel. The effect of film thickness and annealing on contact resistance is investigated. Ultralow contact resistivity $\rho _{c}\approx {1.3} \times {10}^{-{9}} \Omega \, \text {cm}^{{2}}$ and current transfer length ${L}_{T} \approx {2} \text { nm}$ are achieved in a 1-nm-thick film. The superior ohmic contact is made possible by the charge neutrality level (CNL) deeply aligned inside the conduction band for In2O3. Together with theoretical calculations, the Landauer quantum resistance limit of In2O3 is discussed. Furthermore, the ALD-grown In2O3 transistor is back-end-of-line (BEOL) compatible with a low thermal budget of 400 °C (even considering the optional O2 annealing). Our work demonstrates that In2O3 is also an up-and-coming candidate for ultra-scaled, high-performance BEOL transistors from even the contact engineering point of view.

In this work, the transient thermal and electrical characteristics of top-gated (TG), ultrathin, atomic-layer-deposited (ALD), back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors on various thermally conductive substrates are co-optimized by visualization of the self-heating effect (SHE) utilizing an ultrafast high-resolution (HR) thermo-reflectance (TR) imaging system and overcome the thermal challenges through substrate thermal management and short-pulse measurement. At the steady-state, the temperature increase ( $\Delta {T}$ ) of the devices on highly resistive silicon (HR Si) and diamond substrates are roughly 6 and 13 times lower than that on a SiO2/Si substrate, due to the much higher thermal conductivities ( $\kappa $ ) of HR Si and diamond. Consequently, the ultrahigh drain current ( ${I}_{D}$ ) of 3.7 mA/ $\mu \text{m}$ at drain voltage ( ${V}_{\text {DS}}$ ) of 1.4 V with direct current (dc) measurement is achieved with TG ALD In2O3 FETs on a diamond substrate. Furthermore, transient thermal study shows that it takes roughly 350 and 300 ns for the devices to heat-up and cool-down to the steady-states, being independent of the substrate. The extracted thermal time constants of heat-up ( $\tau _{h}$ ) and cool-down ( $\tau _{c}$ ) processes are 137 and 109 ns, respectively. By employing electrical short-pulse measurement with a pulsewidth ( ${t}_{\text {pulse}}$ ) shorter than $\tau _{h}$ , the SHE can be significantly reduced. Accordingly, a higher ${I}_{D}$ of 4.3 mA/ $\mu \text{m}$ is realized with a 1.9-nm-thick In2O3 FET on HR Si substrate after co-optimization. Besides, to integrate BEOL-compatible ALD In2O3 transistors on the front-end-of-line (FEOL) devices with the maintenance of the satisfactory heat dissipation capability, a FEOL-interlayer-BEOL structure is proposed where the interlayer not only electrically isolates the FEOL and BEOL devices but also serves as a thermally conductive layer to alleviate the SHE.

In this work, a thin layer of hexagonal boron nitride (h-BN) or HfO2 serves as an adhesion layer between the ultrathin atomic-layer-deposited (ALD) indium oxide (In2O3) channel and a sapphire substrate to enhance the thermal interfacial conductance. A thermo-reflectance (TR) measurement system with high spatial resolution is introduced to experimentally demonstrates the improvement. With the thin h-BN or HfO2 interlayer, the temperature elevation ( $\Delta {T}$ ) induced by self-heating effect (SHE) is decreased by roughly 9% or 27%, respectively. To quantify the improvement of the interfacial heat transfer, a steady-state thermal diffusion model with a finite-element method is combined with the experimental TR observation to extract the effective thermal boundary conductance (TBC) values in each case. It is shown that the effective TBC is ameliorated by a factor of 2 or 7 with the h-BN or HfO2 interlayer, which is responsible for the $\Delta {T}$ reduction. Furthermore, phonon density of states (PDOS) distribution mismatch implies that the intersection over union (IOU) ratio in the acoustic phonon region of In2O3 with h-BN or HfO2 is roughly 3 or 11 times higher than that directly with sapphire, which is responsible for the profound TBC enhancement. Based on this, ultrahigh maximum drain current of 2.4 mA/ $\mu \text{m}$ is achieved with 2.1-nm-thick In2O3 channel on a sapphire substrate with an HfO2 interlayer in between due to the alleviated SHE.

Ultrathin In2O3 and other recently explored low-thermal-budget ultrathin oxide semiconductors have shown great promise for back-end-of-line (BEOL)-compatible logic layers and monolithic 3-D (M3-D) integration. However, the long-term stability and reliability of these defect-rich atomically thin channels have not been intensively explored yet. Here, we present a study of the long-term reliability of transistors with 1.2-nm-thick atomic-layer-deposited (ALD)-grown In2O3 channels by room-temperature positive bias instability (PBI) and negative bias instability (NBI) experiments. The observed behavior can be largely explained by a trap neutrality level (TNL) model. A route to reduce the parameter drift has been developed using encapsulation in sequence with ${V}_{T}$ engineering by an O2 plasma treatment. After treatment, the magnitude of long-term ${V}_{T}$ shift is reduced for both positive and negative gate bias stresses, and for negative bias stress, other transistor parameters are stabilized as well. In all cases, the subthreshold swing (SS) does not change over time, suggesting that stress-induced interface defects form far below the conduction band, if at all.